Showing papers on "Bipolar junction transistor published in 2003"
TL;DR: In this paper, metal-coated elastomeric stamps are used to establish high-resolution electrical contacts to electroactive organic materials, where the features of relief on the stamps define the geometry and separation of electrically independent electrodes that are formed by uniform, blanket evaporation of a thin metal film onto the stamp.
Abstract: Soft contact lamination and metal-coated elastomeric stamps provide the basis for a convenient and noninvasive approach to establishing high resolution electrical contacts to electroactive organic materials. The features of relief on the stamps define, with nanometer resolution, the geometry and separation of electrically independent electrodes that are formed by uniform, blanket evaporation of a thin metal film onto the stamp. Placing this coated stamp on a flat substrate leads to “wetting” and atomic scale contact that establishes efficient electrical connections. When the substrate supports an organic semiconductor, a gate dielectric and a gate, this soft lamination process yields high performance top contact transistors with source/drain electrodes on the stamp. We use this approach to investigate charge transport through pentacene in transistor structures with channel lengths that span more than three decades: from 250 μm to ∼150 nm. We also report some preliminary measurements on charge transport through organic monolayers using the same laminated transistor structures.
158 citations
TL;DR: In this article, it was shown that the conventional field-effect mobility is a good approximation for the local mobility of the charge carriers at the interface, and that in disordered organic field effect transistors, the local charge carrier mobility decreases from the semiconductor/insulator interface into the bulk.
153 citations
Patent•
09 Apr 2003TL;DR: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such as a row line as discussed by the authors.
Abstract: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such a row line By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced
147 citations
Patent•
16 Sep 2003
TL;DR: In this paper, a method and system for controlling the introduction of a species according to a determined concentration profile of a film comprising the species introduced on a substrate is presented, which is based on a bipolar transistor.
Abstract: A method and system for controlling the introduction of a species according to a determined concentration profile of a film comprising the species introduced on a substrate. In one aspect, the method comprises controlling the flow rate of a species according to a determined concentration profile of a film introduced on a substrate, and introducing a film on a substrate, the film comprising the species at a first concentration at a first point in the film and a second concentration different than the first concentration at a second point in the film. Also, a bipolar transistor including a collector layer of a first conductivity type, a base layer of a second conductivity type forming a first junction with the collector layer, and an emitter layer of the first conductivity type forming a second junction with the base layer. An electrode configured to direct carriers through the emitter layer to the base layer and into the collector layer is also included. In one embodiment, at least one of the first junction and the second junction is between different semiconductor materials to form at least one heterojunction. The heterojunction has a concentration profile of a semiconductor material such that an electric field changes in an opposite way to that of a mobility change.
146 citations
TL;DR: In this article, a new de-embedding strategy using a physics-based lumped-element model for the test-structure parasitics calibrated on the frequency-dependent "open" and "short" dummy impedances is described, which reduces the experimental uncertainty on the deembedded figures of merit.
Abstract: The impedance errors remaining after conventional de-embedding for a high-speed transistor and a single-loop inductor test structure are investigated. A new de-embedding strategy using a physics-based lumped-element model for the test-structure parasitics calibrated on the frequency-dependent "open" and "short" dummy impedances is described, which reduces the experimental uncertainty on the de-embedded figures of merit. Using this new "calibrated lumped-element" de-embedding technique, we have been able to increase the "worst-case" values for the quality factor Q of a 0.6-nH 10-GHz single-loop inductor from 15 to 20 and for the f/sub max/ of a high-speed SiGe bipolar transistor from 80 to 110 GHz. The de-embedding technique presented here is of great importance to develop confidence in on-wafer S-parameter measurements taken at ever increasing microwave frequencies.
127 citations
Book•
07 May 2003
TL;DR: The BSIM4 MOSFET model as mentioned in this paper has been used for accurate distortion analysis of passive devices in CMOS technologies, and the EKV model has also been used to model process variations and device mismatches.
Abstract: Preface. MOSFET Device Physics and Operation. MOSFET Fabrication. RF Modeling. Noise Modeling. Proper Modeling for Accurate Distortion Analysis. The BSIM4 MOSFET Model. The EKV Model. Other MOSFET Models. Bipolar Transistors in CMOS Technologies. Modeling of Passive Devices. Effects and Modeling of Process Variation and Device Mismatch. Quality Assurance of MOSFET Models. Index.
117 citations
Patent•
16 Dec 2003
TL;DR: A bipolar transistor formed in a substrate includes a collector, a base layer above the collector, where the base layer includes a base that is monocrystalline, and an emitter layer that is polysilicon or silicon-germanium as mentioned in this paper.
Abstract: A bipolar transistor formed in a substrate includes a collector, a base layer above the collector, where the base layer includes a base that is monocrystalline, and an emitter layer that is monocrystalline and above the base, where the emitter layer includes silicon or silicon-germanium. An intermediate layer is above the base layer and below the emitter layer. The intermediate layer includes silicon carbide. The intermediate layer is grown epitaxially and is etchable in a dry plasma relative to the emitter layer.
116 citations
TL;DR: A magnetic bipolar transistor is a bipolar junction transistor with one or more magnetic regions, and/or with an externally injected nonequilibrium (source) spin this article, and it is shown that electrical spin injection through the transistor is possible in the forward active regime.
Abstract: A magnetic bipolar transistor is a bipolar junction transistor with one or more magnetic regions, and/or with an externally injected nonequilibrium (source) spin. It is shown that electrical spin injection through the transistor is possible in the forward active regime. It is predicted that the current amplification of the transistor can be tuned by spin.
109 citations
Book•
02 Dec 2003
TL;DR: In this paper, the physics, materials science and technology of silicon bipolar transistors and SiGe BiCMOS transistors are described in a unified manner, and a unified view of the new developments in bipolar technology is presented.
Abstract: Remarkable developments in bipolar technology over the past decade have seen the silicon germanium heterojunction bipolar transistor emerge from research labs to enter production in radio frequency technologies. These developments have allowed SiGe BiCMOS transistors to address high frequency wireless and optical communications applications that were previously only possible in III/V and II/VI devices. This book brings together for the first time all the new developments and describes in a unified manner the physics, materials science and technology of silicon bipolar transistors and SiGe heterojunction bipolar transistors.
107 citations
TL;DR: Bipolar transistors with a ferromagnetic base are shown theoretically to have the potential to generate almost 100% spin-polarized current injection into nonmagnetic semiconductors.
Abstract: Bipolar transistors with a ferromagnetic base are shown theoretically to have the potential to generate almost 100% spin-polarized current injection into nonmagnetic semiconductors. Optical control of ferromagnetism and spin splitting in the base can lead to either long-lived or ultrafast switching behavior. Fringe field control of the base magnetization could be used for information transfer between metallic magnetoelectronics and conventional semiconducting electronics.
104 citations
Patent•
12 May 2003TL;DR: An electrostatic discharge (ESD) MOS transistor (400) including a plurality of interleaved fingers is formed in an I/O periphery of and integrated circuit (IC) (100) for providing ESD protection for the IC.
Abstract: An electrostatic discharge (ESD) MOS transistor (400) including a plurality of interleaved fingers (304), where the MOS transistor (400) is formed in an I/O periphery of and integrated circuit (IC) (100) for providing ESD protection for the IC (100). The MOS transistor (400) includes a P-substrate (402) and a Pwell (406) disposed over the P-substrate (402). The plurality of interleaved fingers (304) each include an N+ source region (320), an N+ drain region (322), and a gate region (324) formed over a channel region (421) disposed between the source (320) and drain regions (322). Each source (320) and drain (322) includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region (324) defined under minimum design rules for core functional elements of the IC. The Pwell (406) forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger (304) of the MOS transistor (400) during an ESD event.
TL;DR: In this article, the authors introduce a source-gated transistor that overcomes some of the fundamental limitations of the field-effect transistor, which can operate at lower voltages with larger gains and lower power dissipation.
Abstract: The thin-film transistor is one of a family of field-effect transistors. They all operate in the same way: a gate modulates the conductance of a channel and the current saturates when the drain end is depleted of carriers. The authors introduce a source-gated transistor that overcomes some of the fundamental limitations of the field-effect transistor. The gate controls the supply of carriers and the current saturates when the source is depleted of carriers. The result is a thin-film transistor that can operate at lower voltages with larger gains and lower power dissipation. It should also preserve its characteristics with smaller dimensions.
TL;DR: In this paper, an exact model for a single-electron transistor was developed within the circuit simulation package SPICE, which uses the orthodox theory of singleelectron tunneling and determines the average current through the transistor as a function of the bias voltage, the gate voltage, and the temperature.
Abstract: An exact model for a single-electron transistor was developed within the circuit simulation package SPICE. This model uses the orthodox theory of single-electron tunneling and determines the average current through the transistor as a function of the bias voltage, the gate voltage, and the temperature. Circuits including single-electron transistors, field-effect transistors (FETs), and operational amplifiers were then simulated. In these circuits, the single-electron transistors provide the charge sensitivity while the FETs tune the background charges, provide gain, and provide low output impedance.
IBM1
TL;DR: In this paper, a model was developed to predict the damage at the Si-SiO/sub 2/ interface, where the base-emitter junction is forward biased, while the collector-base junction is reverse biased under avalanche conditions.
Abstract: SiGe heterojunction bipolar transistors (HBTs) have been investigated under accelerated avalanche stress conditions, where the base-emitter junction is forward biased, while the collector-base junction is reverse biased under avalanche conditions. The high energy avalanche carriers (hot carriers) introduce damage at Si-SiO/sub 2/ interfaces and degrade the characteristics of the SiGe HBTs. A new model has been developed to predict the damage at the Si-SiO/sub 2/ interface. The DC degradation of the base current is shown to correlate with the injected charge total and corresponding energy. The change of base current dependence on avalanche charges and applied voltage is shown, and a model is used to predict the parameter degradation within a typical digital switching application. The impact of this degradation mechanism to f/sub T/ has also been studied and found not to be significant.
01 Feb 2003
TL;DR: Golio et al. as discussed by the authors proposed a nonlinear Transistor Modeling for Circuit Simulation (NTMS) for circuit simulation, and demonstrated the nonlinear transistor model with high voltage and low power.
Abstract: Varactors, Jan Stake Schottky Diode Frequency Multipliers, Jack East Transit Time Microwave Devices, Robert J. Trew Bipolar Junction Transistors, John C. Cowles Heterostructure Bipolar Transistors, William Liu Metal-Oxide-Semiconductor Field Effect Transistors, Leonard MacEachern, Tajinder Manku Metal Semiconductor Field Effect Transistors, Michael S. Shur High Electron Mobility Transistors, Prashant Chavarkar, Umesh Mishra RF Power Transistors from Wide Bandgap Materials, Karen E. Moore Monolithic Microwave IC Technology, Lawrence P. Dunleavy Semiconductors, Mike Harris Metals, Mike Golio RF Package Design and Development, Jeanne S. Pavio Thermal Analysis and Design of Electronic Systems, Avram Bar-Cohen, Karl J. Geisler, Allan D. Krauss Low Voltage/Low Power Microwave Electronics, Mike Golio Technology Computer Aided Design, Peter A. Blakey Nonlinear Transistor Modeling for Circuit Simulation, Walter R. Curtice
TL;DR: In this paper, a self-aligned SiGe heterojunction bipolar transistor (HBT) and SiGe HBTs with CMOS transistors (SiGe BiCMOS) have been developed for use in optical transmission and wireless communication systems.
Abstract: Technologies for a self-aligned SiGe heterojunction bipolar transistor (HBT) and SiGe HBTs with CMOS transistors (SiGe BiCMOS) have been developed for use in optical transmission and wireless communication systems. n-Si cap/SiGe-base multilayer fabricated by selective epitaxial growth (SEG) was used to obtain both high-speed and low-power performance for the SiGe HBTs. The process except the SEG is almost completely compatible with well-established Si bipolar-CMOS technology, and the SiGe HBT and BiCMOS were fabricated on a 200-mm wafer line. High-quality passive elements, i.e., high-precision poly-Si resistors, a high-Q varactor, an MIM capacitor, and high-Q spiral inductors have also been developed to meet the demand for integration of the sophisticated functions. A cutoff frequency of 130 GHz, a maximum oscillation frequency of 180 GHz, and an ECL gate-delay time of 5.3 ps have been demonstrated for the SiGe HBTs. An IC chipset for 40-Gb/s optical-fiber links, a single-chip 10-Gb/s transceiver large-scale IC (LSI), a 5.8-GHz electronic toll collection transceiver IC, and other practical circuits have been implemented by applying the SiGe HBT or BiCMOS technique.
Patent•
10 Jan 2003
TL;DR: In this paper, a semiconductor device is provided with a substrate including a first conductive impurity, a first semiconductor region formed on the semiconductor substrate and including a second conductivity impurity and an interposed semiconductor layer formed at the junction of the second and third semiconductor regions.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device capable of easily regulating a current amplification factor hFE and a withstand voltage between a collector and an emitter without affecting to another semiconductor element, and to provide its manufacturing method. SOLUTION: The semiconductor device is provided with a semiconductor substrate including a first conductive impurity, a first semiconductor region formed on the semiconductor substrate and including a second conductive impurity, a third semiconductor region formed on the first semiconductor region so as to surround the circumference by a second semiconductor region including the first conductive impurity while including the second conductive impurity, a buried semiconductor region formed in the first semiconductor region immediately below the second semiconductor region and including the second conductive impurity whose concentration is higher than the first semiconductor region, and an interposed semiconductor layer formed at the junction of the second semiconductor region and the first semiconductor region, while including the second conductive impurity whose concentration is higher than the first semiconductor region. A vertical bipolar transistor employs the third semiconductor region as an emitter, and employs the second semiconductor region as a base while employing the buried semiconductor region as a collector. COPYRIGHT: (C)2008,JPO&INPIT
TL;DR: In this article, a broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response.
Abstract: Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallel-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.
IBM1
TL;DR: In this paper, SiGe HBT transistors achieving over 200 GHz f/sub T/T/ and F/sub MAX/ are demonstrated, demonstrating 4.2-ps ring-oscillator delays.
Abstract: SiGe HBT transistors achieving over 200 GHz f/sub T/ and f/sub MAX/ are demonstrated in this paper. Techniques and trends in SiGe HBT design are discussed. Processing techniques available to silicon technologies are utilized to minimize parasitic resistances and capacitances and thereby establish raw speeds exceeding III-V devices despite the higher mobility in those materials. Higher current densities and greater avalanche currents, which are required for establishing such high performance, are discussed as they relate to device self-heating and reliability and the degradation of the devices. Simple circuit results are shown, demonstrating 4.2-ps ring-oscillator delays.
TL;DR: In this article, a single-electron transistor (SET) and two ultrasmall metal-oxide-semiconductor field effect transistors (MOSFETs) were used to operate at 25 K at the pumping frequency of ∼1 MHz.
Abstract: A silicon-based single-electron pump that operates at much higher temperatures than previous pumps is fabricated on a silicon-on-insulator substrate. The pump consists of one single-electron transistor (SET) and two ultrasmall metal-oxide-semiconductor field-effect transistors (MOSFETs). We exploit, for the operation, the extremely high off-resistance of the MOSFETs. The high resistance enables us to prevent the unwanted injection (emission) of electrons into (from) the SET nearly perfectly and to make the SET work as a pump. The operation is confirmed at 25 K at the pumping frequency of ∼1 MHz.
TL;DR: In this article, the state-of-the-art performance of diamond Schottky diodes at temperatures of up to 1000 °C, as well as diamond field effect transistors (FETs) with boron delta-doped channels and hydrogen-related surface conductive layers are presented.
Abstract: Over the past few years a variety of diamond electron devices have been fabricated, analysed and simulated. This includes Schottky diodes on boron-doped p+ diamond substrates, boron/nitrogen pn-junction diodes, bipolar transistors based on this pn-junction and field effect transistors (FETs) with boron delta-doped channels and hydrogen-related surface conductive layers. Many of the fabricated devices considered here represent the current state-of-the-art in this field. This includes the operation of diamond Schottky diodes at temperatures of up to 1000 °C, as well as diamond FET devices with a cut-off frequency of 30 GHz and channel current densities of 300 mA mm−1. Simulations show that diamond boron delta-doped FETs might yield an RF-output power density of up to 30 W mm−1.
TL;DR: In this article, a 0.35×12µm2 single heterojunction bipolar transistors (SHBTs) are fabricated exhibiting current gain cutoff frequencies, fT of 509 GHz.
Abstract: InP/InGaAs single heterojunction bipolar transistors (SHBTs) are fabricated exhibiting current-gain cutoff frequencies, fT of 509 GHz. The 0.35×12 µm2 devices consist of a 25 nm graded base and a 75 nm collector, have a breakdown BVCEO of 2.7 V, and operate at current densities above 1100 kA/cm2. This work demonstrates clear progress toward a THz transistor.
TL;DR: In this article, the temperature coefficient of 4H-SiC NPN BJT current gain is studied by way of numerical simulations, and it is shown that high base doping concentration is required to obtain a wide range of current density with a negative temperature coefficient.
Abstract: In this paper, the temperature coefficient of 4H-SiC NPN BJT current gain is studied by way of numerical simulations. In general, 4H-SiC NPN BJT would have a positive temperature coefficient (PTC) for the common emitter current gain if the acceptor ionization energy is smaller than 170 meV. Both PTC and negative temperature coefficient (NTC) can occur in 4H-SiC NPN BJT with an aluminum-doped base. High base doping concentration is required to obtain a wide range of current density with a NTC for current gain, especially when the electron lifetime in base is low. For a base doping concentration of 2.5×10 17 cm −3 , the NTC for current gain is obtained for current density up to 300 A/cm 2 , even when the electron lifetime is as low as 48 ns. The experimental results are also reported.
TL;DR: In this paper, the application of emitter degeneration increases the oscillation frequency while improving the output phase noise and tuning range of LC oscillators designed using bipolar transistors design methodology.
Abstract: This paper provides an analysis on how the application of emitter degeneration increases the oscillation frequency while improving the output phase noise and tuning range of LC oscillators designed using bipolar transistors Design methodology, simulation results and circuit examples for LC oscillators employing this technique are given
Patent•
05 Dec 2003TL;DR: In this article, a bipolar junction transistor (BJT) was proposed for applications in an electrostatic discharge (ESD) protection circuit, where the first well is collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter.
Abstract: A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second well, wherein the first well, the second well, and the first doped region collectively form a parasitic bipolar junction transistor (BJT), and wherein the first well is the collector of the BJT, the second well is the base of the BJT, and the first doped region is the emitter of the BJT.
01 Jan 2003
TL;DR: In this paper, a SiGe bipolar technology for future high frequency applications is presented, with a cut-off frequency of 206 GHz and a maximum oscillation frequency of 197 GHz combined with a gate delay of 3.9 ps.
Abstract: A SiGe bipolar technology for future high frequency applications is presented. A cut-off frequency of 206 GHz and a maximum oscillation frequency of 197 GHz combined with a gate delay of 3.9 ps have been obtained. With a 86 GHz static frequency divider and a 110 GHz dynamic frequency divider state of the art high-speed circuits are achieved.
Patent•
21 Aug 2003TL;DR: In this article, the authors present a manufacturing method of a semiconductor device, which comprises exposing a surface of the semiconductor substrate on which a heterocrystalline layer is to be grown inside of a second emitter opening portion of a hetero-junction bipolar transistor, removing water by preheat treatment in a reducing gas atmosphere, subjecting the substrate to second heat treatment in an atmosphere at a temperature which is higher than the preheating treatment but does not adversely affect the impurity concentration distribution of another element on the substrate, thereby removing an oxide film formed on
Abstract: Provided is a manufacturing method of a semiconductor device, which comprises exposing a surface of a semiconductor substrate on which a heterocrystalline layer is to be grown inside of a second emitter opening portion of a hetero-junction bipolar transistor, removing water by preheat treatment in a reducing gas atmosphere, subjecting the substrate to second heat treatment in a reducing gas atmosphere at a temperature which is higher than the preheating treatment but does not adversely affect the impurity concentration distribution of another element on the semiconductor substrate, thereby removing an oxide film formed on the surface on which the heterocrystalline layer is to be grown, and then selectively causing epitaxial growth of the heterocrystalline layer on the thus cleaned surface in the second emitter opening portion. According to the present invention, reliability of a semiconductor device having a hetero-junction bipolar transistor can be improved.
TL;DR: In this article, a Si-based light modulator working at the standard communication wavelength of 1.5 /spl mu/m has been described, which consists of a threeterminal bipolar mode field effect transistor integrated with a silicon rib waveguide on epitaxial Si wafers.
Abstract: We have fabricated and characterized a novel Si-based light modulator working at the standard communication wavelength of 1.5 /spl mu/m. It consists of a three-terminal bipolar mode field effect transistor integrated with a silicon rib waveguide on epitaxial Si wafers. The modulator optical channel is embodied within its vertical electrical channel. Light modulation is achieved moving a plasma of carriers inside and outside the optical channel by properly biasing the control electrode. The carriers produce an increase of the Si absorption coefficient. The devices have been fabricated using clean-room processing. Detailed electrical characterization and device simulations confirm that strong conductivity modulation and plasma formation in the channel are achieved. The plasma distribution in the device under different bias conditions has been directly derived from emission microscopy analyses. The device performances in terms of modulation depth will be presented.
IBM1
TL;DR: In this article, an accelerated-current wafer-level stress was conducted on 120 GHz SiGe heterojunction bipolar transistors, with stress current density up to as high as J/sub C/=34 mA/spl mu/m/sup 2.
Abstract: As device scaling for higher performance bipolar transistors continues, the operation current density increases as well. To investigate the reliability impact of the increased operation current density on Si-based bipolar transistors, an accelerated-current wafer-level stress was conducted on 120-GHz SiGe heterojunction bipolar transistors (HBTs), with stress current density up to as high as J/sub C/=34 mA//spl mu/m/sup 2/. With a novel projection technique based on accelerated-current stress, a current gain shift of less than /spl sim/15% after 10/sup 6/ h of operation is predicted at T=140/spl deg/C. Degradation mechanisms for the observed dc parameter shifts are discussed for various V/sub BE/ regions, and the separation of the current stress effect from the self-heating effect is made based on thermal resistance of the devices. Module-level stress results are shown to be consistent with wafer-level stress results. The results obtained in this work indicate that the high-speed SiGe HBTs employed for the stress are highly reliable for long-term operation at high operation current density.