Showing papers on "Diffusion capacitance published in 2016"

56 Gb/s Germanium Waveguide Electro-Absorption Modulator

Abstract: We report a Germanium waveguide electro-absorption modulator with electro-optic bandwidth substantially beyond 50 GHz. The device is implemented in a fully integrated Si photonics platform on 200 mm silicon-on-insulator wafers with 220 nm top Si thickness. Wide open eye diagrams are demonstrated at 1610 nm operation wavelength for nonreturn-to-zero on-off keying (NRZ-OOK) modulation at data rates as high as 56 Gb/s. Dynamic extinction ratios up to 3.3 dB are obtained by applying drive voltages of 2 V peak-to-peak, along with an optical insertion loss below 5.5 dB. The device has a low junction capacitance of just 12.8 fF, resulting in 12.8 fJ/bit of dynamic and ∼1.2 mW of static power consumption in typical operating conditions. Wafer-scale performance data are presented and confirm the manufacturability of the device. The demonstrated modulator shows great potential for realizing high-density and low-power silicon photonic transceivers targeting short-reach optical interconnects at serial data rates of 56 Gb/s and beyond.

A new absolute noise thermometer at low temperatures

Abstract: Varactor Diode Amplifier at Liquid Helium Temperature* Previous experiments with parametric amplifiers” have indicated that the effec- tive input noise temperature of the amplifier can be sL1bstantially reduced by refrigerat- ing the amplifier down to liquid nitrogen temperature. It was also found that the noise temperature of the amplifier with a gallium-arsenide diode decreased almost linearly as the amplifier temperature was lowered from room temperature to 40°K.3 Our recent investigations of the junction capacitance of gallium-arsenide diodes have shown that the change in junction capaci- tance from liquid nitrogen temperature to liquid helium temperature is much smaller than that from room temperature to liquid nitrogen temperature; similar results have also been obtained with some epitaxial sili- con diodes. It has also been found that the dynamic quality factor (3 of gallium-ar- senide diodes improves continuously down * Received October 26, 1962. 1 M. Uenohara, “An extremely~low—noise 6—Gc non~ degenerate parametric amplifier,” PROC. IRE (Cor- respondence), vol. 50, pp. 208-209; February, 1962. 2 M. Uenohara, M. Chruney, K. M. Eisele, D. C. Hanson and A. L. Stillwell, “4 Gc Parametric Ampli- fier for Satellite Communication Ground Station Re- ceiver,” presented at the 1962 WESCON,Convention, Los Angeles, Calif.; August 21-24. 3 M. Uenohara, “Noise Characteristics of Refriger- ated Degenerate Variable Capacitance Amplifier at 6 Ge,” Bell Telephone Labs, Inc., Murray Hill, N. J.. BTL Internal Memo., Sept., 1961 (unpublished). Fig. l-Input impedance loci of 4-Gc parametric am- plifier as a function of bias voltage. the amplifier for the Telstar ground station receiver.’ The external idler load is re- moved, however, to accommodate the am- plifier to an available helium dewar. The input frequency is 4.17 Gc and the pump frequency is 23 Ge. The varactor diode used in this amplifier is the gallium-arsenide point-contact diode originally developed by W. M. Sharpless and further developed by N. C. Vanderwal.” The experimental re- sults are tabulated in Table I. The accuracy of noise—temperature meas- urement is believed to be i3°K. The noise figure of the mixer and IF amplifier was 8.3 db and the theoretical noise temperature was calculated based on the measured R,/R...’ The pump power required for 20-db gain was 30 mw at the input of the dewar. The pump circuit was tuned from outside the dewar and only a few milliwatts were dis- sipated in the amplifier. Fig. 2——Photograph of 4~Gc parametric amplifier. to liquid helium temperature. Blake and others at the MIT Lincoln Laboratory have recently measured 10°K excess noise tem- perature for an L-band parametric amplifier operated at liquid helium temperature.‘ This correspondence presents the experimental results of a 4-Gc parametric amplifier at liquid helium temperature. The input impedance loci of the 4-Gc amplifier with a gallium-arsenide diode measured at three different temperatures, i.e., 298°K, 77°K and 4.2°K, as a function of bias voltage are shown in Fig. 1. All three impedance loci were measured at 4.17 Gc with all circuit conditions maintained constant for the entire experiment. Notice that the resonant bias voltage shifted from -1.25 V at 298°K to -0.94 v at 77°K and to -0.85 v at 4.2°K. From the capacitance measured at room temperature and the data in Fig. 1, one can determine the efi°ec— tive diode capacitance at each temperature. The series resistance R, also decreased as the temperature was lowered to liquid helium temperature, as is shown by the increase in the VSVVR at the resonant point as the temperature is reduced. The 4-Gc nondegenerate parametric am- plifier was operated successfully at liquid helium temperature. The effective input noise temperature of the amplifier, including the insertion loss of the room—temperature circulator and a 17-inch-long input Coaxial line, was less than 24°K; of this, only 2°K is believed to be due to the amplifier itself. Fig. 2 shows a photograph of the amplifier. The amplifier mount is identical to that of 4C. Blake, L. VV. Bowles, E. P. McCurley and J. A. Nuttal, “Helium cooled parametric amplifier,” J. Appl. Phys. Letl., to be published. TABLE I Amplifier temperature (°K) 298 77 4.2 Dynamic quality factor Or at 4.17 Ga 9.4 11.6 12.0 Normalized generator im- pedance R0/R3 5.0 5.4 5.9 Measured over-all noise tem- perature (°K) at 20 db gain 192 79 42 30 db gain 24.5 35 db gain 23.5 Noise temperature, paramp only (with 17q line) (°K) 154 46 9.0 Calculated noise temperature at 20-db gain (without 17” line) (°K) 154 38 2.0 In a future experiment, the amplifier to- gether with a circulator will be refrigerated down to liquid helium temperature. We be- lieve that the over-all noise temperature of the parametric amplifier will be as good as that of the maser. The parametric amplifier has definite advantages over the maser, 27.6., broader bandwidth, higher saturation power level, lower pump frequency and power, and a simpler cryogenic system be- cause the operating temperature is not critical. H. J. FINK D. C. HANSON M. UENOHARA Bell Telephone Labs., Inc. Murray Hill, N. J. 5 VV. M. Sharpless, “Gallium-arsenide point-con- tact diodes,” IRE TRANS. ON MICROWAVE THEORY AND TECHNIQUES, vol. MTT—9, pp. 6-10; January, 1961. 6 M. Uenohara, “An extremely low noise 6 Ge nondegenerate parametric amplifier,” I962 I7zle1'nat’l Solid-State Circuit Conf. Digest of Tech. Papers, Lewis Winner, New York, N. Y., pp. 60-61; February, 1962. 7 M. Uenohara and H. Seidel, “961 Me lower side- band up-converter for satellite-tracking radar,” Bell. Sys. Tech. J., vol. 40, pp. 1183-1205; July, 1961.

Bulk FinFETs: Design at 14 nm Node and Key Characteristics

Abstract: In contrast to conventional 2-D MOSFETs, FinFETs are able to be scaled down to 20 nm and beyond, and have superior performance. There are two types of FinFETs:SOI FinFETs and bulk FinFETs. Bulk FinFETs are built on bulk-Si wafers, which have less defect density and are cheaper than SOI wafers, while also having better heat transfer rate to the substrate compared to SOI FinFETs. In 2011, Intel announced the world’s first 3-D transistors in the mass production of a 22 nm microprocessor (code-named Ivy Bridge). The 3-D transistors adopted by Intel are actually bulk FinFETs. In this chapter, we provide the design guidelines for bulk FinFETs at the 14 nm node, and compare bulk and SOI FinFETs in terms of scalability, parasitic capacitance, and heat dissipation. Decrease of the drain current by parasitic resistance in the source (S) and drain (D) regions is also addressed. Drain current fluctuation by single charge trap is studied in terms of the trap depth, trap position, and percolation path. In the design of 14 nm bulk FinFETs, a punch-through stopper at a position just under the S/D junction depth is required to suppress unwanted cross-talk between S and D. The peak concentration of the stopper needs to be 2–3 × 1018 cm−3. The S/D junction depth should be equal or slightly smaller than the height of fin body, defined from the surface of the isolation oxide region to the top of the fin body. Considering the short channel effect and drain current drivability, the reasonable doping concentration of uniformly doped fin body is 2–3 × 1017 cm−3. To keep the drain-induced barrier below 100 mV/V when the length between the S and D junctions is the same as the gate length (14 nm), the width of the fin body should be ~9 nm. Under the same doping concentration and geometry, both 14 nm SOI and bulk FinFETs have nearly the same I–V characteristics, which mean nearly the same scalability. Since thin fin bodies protruding from the substrate are easily depleted, the junction capacitance of the S/D to fin body can be reduced to similar or even lower values than that of SOI FinFETs. To achieve a similar heat transfer rate to the substrate as bulk FinFETs, the buried oxide in SOI FinFETs should be thinned down to 20 nm or beyond, which could cause unwanted increase in the parasitic capacitance. The contact area between the metal electrode and the S/D region should be as wide as possible to reduce the S/D parasitic resistance.

Analytical derivation of DC SQUID response

Abstract: We consider voltage and current response formation in DC superconducting quantum interference device (SQUID) with overdamped Josephson junctions in resistive and superconducting state in the context of a resistively shunted junction (RSJ) model. For simplicity we neglect the junction capacitance and the noise effect. Explicit expressions for the responses in resistive state were obtained for a SQUID which is symmetrical with respect to bias current injection point. Normalized SQUID inductance (where I c is the critical current of Josephson junction, L is the SQUID inductance, e is the electron charge and is the Planck constant) was assumed to be within the range l ≤ 1, subsequently expanded up to using two fitting parameters. SQUID current response in the superconducting state was considered for arbitrary value of the inductance. The impact of small technological spread of parameters relevant to low-temperature superconductor (LTS) technology was studied, using a generalization of the developed analytical approach, for the case of a small difference of critical currents and shunt resistances of the Josephson junctions, and inequality of SQUID inductive shoulders for both resistive and superconducting states. Comparison with numerical calculation results shows that developed analytical expressions can be used in practical LTS SQUIDs and SQUID-based circuits design, e.g. large serial SQIF, drastically decreasing the time of simulation.

Organic diode with high rectification ratio made of electrohydrodynamic printed organic layers

Abstract: In this paper, an all-printed organic diode to reveal a high rectification ratio (∼1.2 × 104) is proposed using organic heterojunction materials N,N′-Bis(3-methylphenyl)-N,N′-diphenylbenzidine (TPD) and fullerene (C60). The proposed organic diode is fabricated as a structure of ITO/TPD/C60/Al on a glass substrate through an all-printed electrohydrodynamic (EHD) technique, which has an effective area of 2 × 2 mm2. The threshold voltage of the forward bias is 1.2 V and the current density reaches 550 mA/cm2 at 3 V. The device is characterized by current voltage I-V at temperature 30°C to 120°C, and junction capacitance is analyzed at 4 kHz frequency at ±2 V. To verify the successful construction of all layers deposited through the EHD technique, morphology analysis was carried out with FE-SEM. From these measured electrical characteristics, suitability for rectification purposes in printed electronics is confirmed.

From MEMRISTOR to MEMImpedance device

Abstract: The behavior of the capacitance switching of HfO2Resistive non-volatile Memories is investigated in view of realizing a MEMImpedance (MEM-Z) device. In such a Metal Insulator Metal structure, the impedance value can be tuned by the adjustment of both resistance and capacitance values. We observe a strong variation of capacitance from positive to negative values in a single layer Metal Insulator Metal device made of HfO2deposited by Atomic Layer Deposition, but unfortunately no memory effect is observed. However, in the case of a two layer structure, a device has been obtained with a memory effect where both resistance and capacitance values can be tuned simultaneously, with a variation of capacitance down to negative values to get an inductive behavior. Negative capacitance values are observed for voltage values near SET voltage. A schematic model based on shaped oxygen vacancy density is proposed to account for this capacitance variation. The oxygen vacancies can be either isolated or connected in the bulk of the oxide.

Characteristics of SiC MOSFET and its application in a phase-shift full-bridge converter

Abstract: With the outstanding advantages of SiC MOSFET, which has lower junction capacitance, low-on-state resistor and high junction operating temperature compared to a Si devices, the converter can achieve a high-frequency and high-efficiency. This increases the power density with smaller volume of passive components and reduced cooling requirements. However, in the phase-leg configuration, high dv/dt will worsen the interference between the two devices during a switching transient (i.e., crosstalk). Unfortunately, SiC power devices are more easily affected by crosstalk than Si devices due to their intrinsic properties. To utilize the full potential of fast SiC devices, a novel and cost-effective gate assist circuit for crosstalk supression is proposed in this paper. Besides, with the increase of power density, the thermal design is increasingly becoming the key factor that affects the reliability of converters. Thus, the thermal model of the phase-shift full-bridge converter (PSFBC) is established. The simulation and experimental results are in good agreement, which testifies the accuracy of thermal model. The efficiency of 2kW PSFBC based on Si and SiC MOSFETs under different loads is also measured and compared in this paper.

Review of negative capacitance transistors

Abstract: A ferroelectric material stores energy from phase transition and in doing so it lends itself to be biased at a state where its capacitance is negative [1,2]. When such a negative capacitance is added in series to the gate of a, subthreshold swing in a Field Effect Transistor (FET), it is possible to reduce the subthreshold swing below 60 mV/decade, without changing the transport physics of the FET. Not having to change the transport physics means that the ON current can be high while the supply voltage can be reduced significantly. Therefore, the negative capacitance effect has the potential to lead to very low voltage yet high performance electronic switches.

Influence of the junction capacitance of the secondary rectifier diodes on output characteristics in multi-resonant converters

Abstract: Multi-resonant converters like the CLLLC topology are known for their outstanding efficiency and high power density. Little information has however been published about the influences of secondary side diode junction capacitances on the output characteristics of the resonant converter. This paper presents a detailed analysis of these influences in the inductive working range and reviews practical design considerations of the converter. Therefore, experimental results of an inductive power transfer system, using a CLLLC resonant topology, are compared to theoretical time domain solution, showing significant effects of different semiconductor materials and devices on output power. These effects will be discussed and explained in detail by using measured key waveforms.

3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET

Abstract: Due to increasing bandwidth demand in data centers and telecommunication infrastructures, the maximum data-rate of wireline transceivers is projected to double from 32Gb/s to 64Gb/s while keeping the same power envelope. This paper presents the design of a 64Gb/s NRZ transmitter for short-reach electrical links in a 16nm FinFET process. It is applicable to standards such as CEI-56-VSR/MR, using power efficient techniques that take into considerations FinFET device properties: low DIBL, negligible body effect, low junction capacitance, low channel leakage, high intrinsic gain, high gate capacitance and resistance, high flicker noise, and steep CV curve in accumulation region.

Effect of white LED DC-bias on modulation speed for visible light communications.

Abstract: The light emitting diode (LED) nonlinearities distortion induced degradation in the performance of visible light communication (VLC) systems can be controlled by optimizing the DC bias point of the LED. In this paper, we theoretically analyze and experimentally demonstrate the effect of white LED DC bias on nonlinear modulation bandwidth and dynamic range of the VLC system. The linear dynamic range is enhanced by using series-connected LED chips, and the modulation bandwidth is extended to 40 MHz by post-equalization without using a blue filter. The experimental results well match the theoretical model of LED nonlinear modulation characteristics. The results show that the modulation bandwidth increases and saturates with an increase in LED DC bias current due to nonlinear effect of carrier lifetime and junction capacitance. The optimized DC-bias current that corresponds to the minimum BER increases with the increase of data rate. A 60-Mbps NRZ transmission can be achieved with BER threshold of 10-3 by properly adjusting LED DC bias point.

Characterization of a Drift-Step-Recovery Diode Based on All Epi-Si Growth

Abstract: Drift-step-recovery diodes (DSRDs) are fast-opening switches capable of delivering nanosecond-scale high-voltage (HV) pulses into a load. The HV capability is achieved by stacking DSRD dies in series. In this paper, we characterize a DSRD die based on silicon epitaxial layers, which was designed and manufactured at the Soreq Nuclear Research Center. In the static characterization, we have measured the diode’s forward- and reverse-blocking voltages, and the junction capacitance. In the dynamic characterization, we have measured the peak voltage and its rise time for a single die, and up to a stack of 32 dies in series, where the stack was operated at current densities of up to $\sim \!\!1.3$ kA/cm2. The shortest rise time was 0.65 ns from a stack of five dies. An HV increase of 250 V per die was obtained. The maximum measured peak voltage was 6.09 kV with a rise time of 2.2 ns, and these results being limited by the setup capability.

High-voltage gain zero-current switching push–pull resonant converter for small energy sources

Abstract: This study presents a high-voltage gain zero-current switching (ZCS) push–pull resonant converter for small energy sources. The converter provides a high voltage from a 12 V DC battery via isolated transformer and full-bridge rectifier. The main switches of the push–pull and full-bridge diode rectifier operate under ZCS condition. The advantage of this technique is the use of leakage inductance for ZCS operation of the power switch and in designing the secondary side of a resonant tank. A prototype high-voltage gain push–pull resonant converter was built and operated at 110 kHz fixed switching frequency, 350 V DC output voltage, and 200 W output power to analyse the effect of parasitic junction capacitance of the full-bridge rectifier, which significantly affects the operating point of the resonant tank and the voltage. This study introduces the implementation and design using the data of a single diode to calculate the parameters. The simulation and experimental results verified the proposed and designed circuits. Both results agreed with the theoretical analysis.

Controlling the screening process of a nanoscaled space charge region by minority carriers

Abstract: The miniaturization of future electronic devices is intimately connected to the ability to control electric fields on the atomic scale. In a nanoscopic system defined by a limited number of charges, the combined dynamics of bound and free charges become important. Here we present a model system based on the electrostatic interaction between a metallic tip of a scanning tunnelling microscope and a GaAs(110) semiconductor surface. The system is driven out of equilibrium by optical excitation, which provides ambipolar free charge carriers, and by an optically induced unipolar tunnel current. This combination enables the active control of the density and spatial distribution of free and bound charge in the space-charge region, that is, modifying the screening processes. Temporal fluctuations of single dopants are modified, meaning we are able to control the noise of the system. It is found that free charge carriers suppress the noise level in field-controlled, nanoscopic systems.

Improvements in and relating to drivers

Abstract: A driver circuit for an LED display for switching a light-emitting diode (LED) between a non-luminous state and a luminous state for producing light for a display, the driver circuit comprising an LED, a drive current controller (10) arranged to selectively open and close a drive current flow path (8) through the LED (2) thereby selectively to switch the LED between a non-luminous state and a luminous state, a charge injector unit (13) for inputting charge into the LED to store said charge within the LED via the junction capacitance (3) thereof, a control unit (12) arranged to control the charge injector unit to input said charge into the LED concurrently with the opening of the drive current flow path.

Common mode filter for USB 3 interfaces

Abstract: This paper presents an integrated common mode filter (CMF) for USB 3 interfaces that are operated in SuperSpeed mode. For the protection of sensitive USB ports against Electrostatic Discharge (ESD) this filter device includes an advanced low-voltage triggered semiconductor controlled rectifier (LVTSCR). Compared to conventional ESD protection diodes, LVTSCR offer a very low junction capacitance (only 0.20 pF) and a low clamping voltage due to the low dynamic resistance (0.14 Ohm). The manufacturing process combines planar layers of copper and polyimide on top of bipolar silicon wafer. The integrated Cu-air coils obviate the need for additional ferrites for common mode suppression. The −3 dB passband frequency for the differential mode is 6 GHz, while the common mode exhibits a strong attenuation of frequencies above 1GHz (>15 dB). A distinctive notch characteristic for the common mode is visible between 2 GHz and 3 GHz (typ. >30 dB). This makes the device suitable for applications where USB 3.1, Gen 1 and 2.4 GHz WIFI (802.11 b/g/n) are implemented in close vicinity. Due to the small size (0.8 mm by 1.2 mm) the device is beneficial in portable applications like smartphones.

Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor

Abstract: Quantum capacitance is expected to have strong impact on the gate capacitance in III-V devices. In this paper, we present a comprehensive analysis of the quantum capacitance for III-V ultra-thin body with thin box transistor. The results show the presence of quantum capacitance effect and step like behavior due to individual contribution of sub-bands in the gate capacitance. We discuss the impact of various parameters such as insulator thickness, channel (body) thickness on the capacitance with positive and negative back gate biases.

A Multiregion Approach to Modeling the Base-Collector Junction Capacitance

Abstract: The junction capacitance of heterojunction bipolar transistors (HBTs) is commonly modeled based on the theory of the p-n-homojunction with constant doping levels, made more flexible by the introduction of adjustable model parameters. In III–V HBTs, however, the low-doped collector is often not uniform, but contains both material and doping steps used to suppress the collector current blocking and to improve the linearity. Under these circumstances, the classical formulation is not sufficient to model the capacitance. Similarly, the exponential spatial doping dependence in the collector of modern high-speed HBTs may require a more in-depth approach. In this brief, a smooth expression for modeling the junction capacitance of a multiregion layer stack is presented. The accuracy of the new model is demonstrated based on both simulated and measured data.

Ringing frequency extraction for health monitoring of power transistors

Abstract: The detection, diagnostic, and prognostic of power transistor degradation play a key role in increasing the reliability and safety of power electronic converters (PECs), especially in aeronautic and astronautic fields. In a PEC, high-frequency oscillation may occur during the switching transients of power transistors, which is known as ringing. The switching ringing reflects the intrinsic parameters of power transistors. Evaluating the change over time of these parameters characterized from ringing becomes a key indicator to assess the aging status of the PEC with respect to transistor degradation. The leg midpoint voltage (ν M ) is often used to capture the ringing information. However, dc offset voltage and numerous harmonics in ν M make it difficult to acquire useful information. In this paper, the voltage across the stray inductance is used to extract the ringing waveform during transistor switching, and the fast Fourier transform is used to capture the ringing frequency. The measured ringing frequency is associated with transistor's junction capacitance or internal parasitic inductance, and the detected shifts in frequency can indicate transistor degradation.

Effect of junction recombination velocity of electrical parameters of a vertical parallel silicon solar cell under frequency modulation

Abstract: This study investigates a theoretical study based on the determination of electrical parameters in solar cell junction vertical parallel silicon under polychromatic illumination and frequency modulation. From the excess minority carrier’s density in the solar cell, the photocurrent density and the photovoltage are derived. The route of the current voltage density (I = f(V)) that materializes the behavior of the generator; we have a model on the shunt resistance and the series resistance. The I–V method is used to determine electrical parameters such as resistance and shunt resistance or various junction recombination velocity. From their expressions, we study their pace according to Bode and Nyquist and then extend the study to other electrical parameter. The Bode diagrams of the diffusion capacitance are shown for different junction recombination velocity.

Submodule integrated boost DC-DC converters with no external input capacitor or input inductor for low power photovoltaic applications

Abstract: This paper proposes to utilize the internal solar cell diffusion capacitance and internal solar module wire parasitic inductances to replace the input capacitor and filter inductor in boost derived DC-DC converters for energy harvesting applications. High switching frequency (MHz) hard switched and resonant boost converters are proposed. Analysis, simulation and experimental prototypes are presented. A specific proof-of-concept application is especially tested for foldable photovoltaic (PV) panels, which are known for their high internal wire inductance. The experimental converters successfully boost solar module voltage without adding any external input capacitance or filter inductor.

Monitoring Test Structure for Plasma Process-Induced Charging Damage Using Charge-Based Capacitance Measurements

Abstract: A novel monitoring test structure is proposed for plasma process-induced charging damage (PID) based on charge-based capacitance measurement (CBCM), referred to as PID–CBCM. By eliminating antenna capacitance interferences, a remarkably smaller gate capacitance (tens of fF) can be obtained for effectively evaluating the influence of PID on metal oxide semiconductor field-effect transistors (MOSFETs). Moreover, the interface trap density can be extracted simultaneously using PID–CBCM implemented with modified charge pumping measurements. Furthermore, another type of PID–CBCM structure under unique measurement conditions has been developed to evaluate drain current (Id) as a function of gate voltage (Vg). The new structure works by extracting the threshold voltage (Vth) shifts on the basis of capacitance–voltage (C–V) characteristics after applying a stress voltage to the gate oxide of devices under test in the PID–CBCM structure. Based on these approaches, three meaningful characteristics of the PID are obtained: 1) Vth shifts extracted from C–V characteristics; 2) Vth shifts extracted from Id–Vg characteristics; and 3) interface trap density extracted from charge-pumping current. Thus, the effects of PID on MOSFET can be monitored over suitably small areas such as scribe-line and chip areas.

Analytical Description of the Input Capacitance of 4H-SiC DMOSFET’s in Presence of Oxide-Semiconductor Interface Traps

Abstract: An analytical model of the input capacitance of Vertical DMOSFETs in 4H-SiC is presented, in order to provide an accurate instrument for the quantitative analysis and synthesis of the device and for accurate interpretations of C-V measurements. The model describes the charge dynamics into the channel and the accumulation region of the device, in presence of the energy dependent oxide-semiconductor interface trapped charge. Comparisons with numerical simulations show that the model correctly describes the variations of the surface potential induced by the gate voltage in all the device regions covered by the oxide, from accumulation to strong inversion of the channel, and to correctly relate them to the capacitance variations.

DISPERSION IN IMPEDANCE SPECTRA OF ISOTYPE CdO–ZnO THIN FILM HETEROSTRUCTURE ON APPLIED DC BIAS

Abstract: Radio frequency magnetron sputtering technique has been used to prepare n–n isotype heterostructure of CdO–ZnO thin film on glass substrate. The energy band structure analysis shows the formation of charge accumulation and charge depletion region created near the interface of CdO–ZnO n–n isotype heterostrucure which leads to the formation of a junction capacitance. The impedance spectroscopic studies of CdO–ZnO isotype heterostructure show an excellent dispersion in the impedance spectra as observed in the Nyquist plot depending on applied DC bias voltage. The frequency response of impedances has been explained from band structure and equivalent electrical circuit model of the heterostructure. These studies will be highly significant in exploring the possibility of application of such isotype interfaces in optimizing the functionality of organic and inorganic electronic devices and solar cells.

Sub-fF-capacitance photonic-crystal photodetector towards fJ/bit on-chip receiver

Abstract: A photonic-crystal photodetector having a <1-fF junction capacitance, 1-A/W responsivity, and 40-Gbit/s eye opening was demonstrated. Its resistor-loaded configuration unveiled a light-to-voltage conversion with a kV/W efficiency without amplifiers, promising for an fJ/bit-energy on-chip receiver.

Analytical derivation of DC SQUID response

Abstract: We consider voltage and current responses formation in DC SQUID with overdamped Josephson junctions in resistive and superconducting state in the frame of resistively shunted junction (RSJ) model. For simplicity we neglect the junction capacitance and the noise effect. Explicit expressions for the responses in resistive state were obtained for a SQUID which is symmetrical with respect to bias current injection point. Normalized SQUID inductance $l = 2 e I_c L/\hbar$ (where $I_c$ is the critical current of Josephson junction, $L$ is the SQUID inductance, $e$ is the electron charge and $\hbar$ is the Planck constant) was assumed to be within the range $l \leq 1$, subsequently expanded up to $l \approx 7$ using two fitting parameters. SQUID current response in superconducting state was considered for arbitrary value of the inductance. Impact of small technological spread of parameters relevant for low-temperature superconductor (LTS) technology was studied with generalization of the developed analytical approach for a case of small difference of critical currents and shunt resistances of the Josephson junctions, and inequality of SQUID inductive shoulders for both resistive and superconducting states. Comparison with numerical calculation results shows that developed analytical expressions can be used in practical LTS SQUIDs and SQUID-based circuits design, e.g. large serial SQIF, drastically decreasing the time of simulation.

Development of Planar Schottky Diode on GaAs Substrate for Terahertz Applications

Abstract: In this paper, we demonstrate the planar Schottky diode on GaAs substrate for terahertz applications A nanoscale dot and T-shaped disk has been developed as the anode for terahertz Schottky diode The low parasitic elements of the nanoscale anode with T-shaped disk yield high cutoff frequency characteristic The fabricated Schottky diode with anode diameter of 500 nm has series resistance of 21 Ω, ideality factor of 132, junction capacitance of 803 fF, and cutoff frequency of 944 GHz

Analysis and simulation of a higher amplitude expansion millimeter wave predistortion linearizer

Abstract: In millimeter wave and upon band, the amount of amplitude expansion of the conventional based on schottky diode predistortion linearizer decrease due to the effect of junction capacitance of the schottky diode. As a result, it becomes very difficult for the predistortion linearizer to compensate gain compression and phase lag of TWTA (traveling wave tube amplifier). So, this paper proposed a new method based on series schottky diode to reduce effect of schottky diode junction capacitance and increase the amount of amplitude expansion of predistortion linearizer. Simulation shows, in 30GHz band, the new predistortion linearizer amplitude expansion increase from 2. 5dB to4dB, phase lead increase from 30 degree to 40 degree in saturation power point.