Showing papers on "Drain-induced barrier lowering published in 2008"

AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications

Abstract: This letter reports normally-off operation of an AlGaN/GaN recessed MIS-gate heterostructure field-effect transistor with a high threshold voltage. The GaN-based recessed MIS-gate structure in conjunction with negative polarization charges under the gate allows us to achieve the high threshold voltage, whereas the low on-state resistance is maintained by the 2-D electron gas remaining in the channel except for the recessed MIS-gate region. The fabricated device exhibits a threshold voltage as high as 5.2 V with a maximum field-effect mobility of 120 cm2/Vmiddots, a maximum drain current of over 200 mA/mm, and a breakdown voltage of 400 V.

A new definition of threshold voltage in Tunnel FETs

Abstract: This work reports on the physical definition and extraction of threshold voltage in Tunnel FETs (field effect transistors) based on numerical simulation data. It is shown that the Tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, VTG, and one in terms of drain voltage, VTD. These threshold voltages can be physically defined based on the transition between a quasi-exponential dependence, and a linear dependence of the drain current on VGS or VDS, and by extension, on the saturation of the tunneling energy barrier width narrowing. The extractions of VTG and VTD are performed based on the transconductance change method in the double gate Tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these Tunnel FETs' threshold voltages, as well as the dependence of VTG on applied drain voltage and VTD on applied gate voltage, are investigated.

Bias stress instability in pentacene thin film transistors: Contact resistance change and channel threshold voltage shift

Abstract: Bias stress instability in top-contact pentacene thin film transistors was observed to be correlated not only to the channel but also to the metal/organic contact. The drain current decay under bias stress results from the combination of the contact resistance change and the threshold voltage shift in the channel. The contact resistance change is contact-metal dependent, though the corresponding channel threshold voltage shifts are similar. The results suggest that the time-dependent charge trapping into the deep trap states in both the contact and channel regions is responsible for the bias stress effect in organic thin film transistors.

Tunnel field-effect transistor with gated tunnel barrier

Abstract: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).

Inversion mode n-channel GaAs field effect transistor with high-k/metal gate

Abstract: Highly effective passivation of GaAs surface is achieved by a thin amorphous Si (a-Si) cap, deposited by plasma enhanced chemical vapor deposition method. Capacitance voltage measurements show that carrier accumulation or inversion layer is readily formed in response to an applied electrical field when GaAs is passivated with a-Si. High performance inversion mode n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with an a-Si/high-k/metal gate stack. Drain current in saturation region of 220mA∕mm with a mobility of 885cm2∕Vs were obtained at a gate overdrive voltage of 3.25V in MOSFETs with 5μm gate length.

Accumulation field effect microelectronic device and process for the formation thereof

Abstract: A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.

A Quasi-Two-Dimensional Compact Drain–Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects

Abstract: A drain-current model for undoped symmetric double-gate MOSFETs is proposed. Channel-length modulation and drain-induced barrier lowering are modeled by using an approximate solution of the 2D Poisson equation. The new model is valid and continuous in linear and saturation regimes, as well as in weak and strong inversions. Excellent agreement was found with Silvaco-ATLAS simulations.

Inversion-channel GaN metal-oxide-semiconductor field-effect transistor with atomic-layer-deposited Al2O3 as gate dielectric

Abstract: Inversion n-channel GaN metal-oxide-semiconductor field-effect-transistors (MOSFETs) using atomic-layer-deposited Al2O3 as a gate dielectric have been fabricated, showing well-behaved drain I-V characteristics. The drain current was scaled with gate length (varying from 1to16μm), showing a maximum drain current of ∼10mA∕mm in a device of 1μm gate length, at a gate voltage of 8V and a drain voltage of 10V. At a drain voltage of 0.1V, a high Ion∕Ioff ratio of 2.5×105 was achieved with a very low off-state leakage of 4×10−13A∕μm. Both MOSFET and MOS capacitor showed very low leakage current densities of 10−8A∕cm2 at biasing fields of 4MV∕cm. The interfacial density of states was calculated to be (4–9)×1011cm−2eV−1 near the midgap.

Minimizing read disturb in an array flash cell

Abstract: A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.

The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs

Abstract: The ground plane (GP) concept is one of the techniques used to reduce the drain-induced barrier lowering (DIBL) in nanoscale MOSFETs and is effective only when the distance between the GP and the drain is small as compared with the channel length. Therefore, if the GP is placed in the substrate (GPS), the buried oxide (BOX) thickness should be kept as small as possible which, however, results in an increased subthreshold slope. As a result, for sub-100-nm channel lengths, it is not possible to achieve both reduced DIBL and steep subthreshold slope using GPS. In this brief, a new device structure with the GP BOX is proposed to overcome the aforementioned shortcomings so that a reduced DIBL as well as an improved subthreshold slope can be obtained. Two-dimensional simulation is used to understand the efficacy of the proposed method.

Tunnel field-effect transistors with superlattice channels

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Gate-Length and Drain-Bias Dependence of Band-to-Band Tunneling-Induced Drain Leakage in Irradiated Fully Depleted SOI Devices

Abstract: The effects of gate length and drain bias on the off-state drain leakage current of irradiated fully-depleted SOI n-channel MOSFETs are reported. The experimental results are interpreted using a model based on the combined effects of band-to-band tunneling (BBT) and the trapped charge in the buried oxide. For negative gate-source voltages, the drain leakage current increases with the drain voltage because the electric field in the gate-to-drain overlap region is increasing. The off-state current in these devices increases with total ionizing dose due to oxide trapped charge build up in the buried oxide, enhanced by the BBT mechanism. The experimental data show that these effects are more significant for devices with shorter gate-lengths. Simulation results suggest that the BBT-generated holes are more likely to drift all the way from the drain to the source in shorter devices, enhancing the drain leakage current, while they tend to tunnel across the gate oxide in longer devices.

Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

Abstract: The novel gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high-performance electrical characteristics and high immunity to short-channel effects (SCEs). The nanowire channel with high body-thickness-to-width ratio (TFin/WFin), which is approximately equal to one, was realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs were also achieved to build the GAA structure. The resultant GAA-MNC TFTs showed outstanding three-dimensional (3-D) gate controllability and excellent electrical characteristics, which revealed a high on/off current ratio ( > 108), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. Therefore, such high-performance GAA-MNC TFTs are very suitable for applications in system-on-panel and 3-D circuits.

Rectifier circuit and radio communication device

Abstract: A rectifier circuit includes a bias circuit that outputs a direct-current voltage; a first MOS transistor that has a gate and a source; and a second MOS transistor that has a gate, a source, and a drain connected to the source of the first MOS transistor. Only the direct-current voltage is applied between the gate and the source of the first MOS transistor, and only the direct-current voltage being applied between the gate and the source of the second MOS transistor. The rectifier circuit also includes a coupling capacitor that has a first end which is connected to the source of the first MOS transistor, and a second end to which an alternating-current signal is input.

JFET Depletion in SuperJunction Devices

Abstract: SuperJunction theory predicts that specific on- resistance improves as the widths of the N- and P-type regions in the drift region are reduced. In this paper, it is shown that there is a practical limit to improving on-resistance by shrinking these widths, due to JFET depletion of the conducting regions. An analytic model is developed to calculate the optimum drift region width for super junction devices, and this model is verified by simulations. Specific examples of optimized drift region widths for superjunction devices with various levels of drift region charge and applied drain voltage are provided.

Method of writing into semiconductor memory device

Abstract: An NMOS transistor 14 having one end connected to one end of a resistance memory element 10 is provided, and when a voltage is applied to the resistance memory element 10 via the NMOS transistor 14 to switch the resistance memory element 10 from the low resistance state to the high resistance state, the gate voltage of the NMOS transistor 14 is set at a value which is equal to or greater than the total of the reset voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14 and is smaller than the total of the set voltage of the resistance memory element 10 and the threshold voltage of the NMOS transistor 14, whereby the voltage applied to the resistance memory element 10 is set at a value which is equal to or greater than the reset voltage and is smaller than the set voltage.

Low vt antifuse device

Abstract: A one time programmable memory cell having an anti-fuse device with a low threshold voltage independent of core circuit process manufacturing technology is presented. A two transistor memory cell having a pass transistor and an anti-fuse device, or a single transistor memory cell having a dual thickness gate oxide, are formed in a high voltage well that is formed for high voltage transistors. The threshold voltage of the anti-fuse device differs from the threshold voltages of any transistor in the core circuits of the memory device, but has a gate oxide thickness that is the same as a transistor in the core circuits. The pass transistor has a threshold voltage that differs from the threshold voltages of any transistor in the core circuits, and has a gate oxide thickness that differs from any transistor in the core circuits. The threshold voltage of the anti-fuse device is lowered by omitting some or all of the threshold adjustment implants that is used for high voltage transistors fabricated in the I/O circuits.

Semiconductor transistor with p type re-grown channel layer

Abstract: The invention is a device for controlling conduction across a semiconductor body with a P type channel layer between active semiconductor regions of the device and the controlling gate contact. The device, often a MOSFET or an IGBT, includes at least one source, well, and drift region. The P type channel layer may be divided into sections, or divided regions, that have been doped to exhibit N type conductivity. By dividing the channel layer into regions of different conductivity, the channel layer allows better control over the threshold voltage that regulates current through the device. Accordingly, one of the divided regions in the channel layer is a threshold voltage regulating region. The threshold-voltage regulating region maintains its original P type conductivity and is available in the transistor for a gate voltage to invert a conductive zone therein. The conductive zone becomes the voltage regulated conductive channel within the device.

Tunneling Current--Voltage Characteristics of Graphene Field-Effect Transistor

Abstract: We develop an analytical device model for a graphene field-effect transistor. Using this model, we calculate its current–voltage characteristics at sufficiently high gate voltages when a n–p–n (p–n–p) lateral junction is formed in the transistor channel and the source–drain current is associated with the interband tunneling through this junction.

Unique carbon-nanotube field-effect transistors with asymmetric source and drain contacts.

Abstract: We have fabricated a type of unique single-walled carbon nanotube field-effect transistor, in which the channel length is only 90 nm and aluminum and gold are used as its drain and source electrodes, respectively. The channel conductance oscillations caused by single-electron tunneling through the asymmetric barriers at the drain and source contacts are observed up to 100 K. Above 100 K, the tunneling fades away, and thermionic emission dominates the conductance at sufficiently negative gate voltages. At room temperature, the device shows diode-like characteristics with a maximum current rectification ratio of similar to 10(4).

Dual material gate oxide stack symmetric double gate MOSFET: Improving short channel effects of nanoscale double gate MOSFET

Abstract: In this paper, short channel effects of the sub-100nm modified symmetric double-gate MOSFET that made of dual material gates and oxide stack with high-k material on top of a SiO2 layer examined and compared with conventional symmetric double-gate MOSFET using two-dimensional (2-D) simulation. This structure reduces short channel effects (SCEs) such as drain-induced barrier lowering (DIBL), hot electron effect and threshold voltage roll-off and has better current characteristics when compared to the conventional double-gate MOSFET.

The Effects of Drain-Bias on the Threshold Voltage Instability in Organic TFTs

Abstract: In this letter, the influence of drain bias on the threshold voltage instability in pentacene-based organic thin-film transistors (OTFTs) was studied. By applying different drain biases to adjust the channel carrier concentration in linear mode, the threshold voltage shift was found to be proportional to the carrier concentration. The experimental data can be well quantitatively explained by the drain bias-stress theory developed for a-Si TFTs. The outcome gives the insight of the degradation mechanism of OTFTs and is important for the design of OTFT pixel circuit, OTFT analog amplifiers, or OTFT active loads.

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET

Abstract: We examined the influence of process variation on device performance of the optimized 10-nm FinFET device using a fully self-consistent quantum-mechanical transport simulator based on the contact block reduction method. Sensitivity of the on-current, leakage currents, threshold voltage, drain-induced barrier lowering, and subthreshold swing for the optimized FinFET to process variation at room temperature have been investigated. Subthreshold source-to-drain leakage current is found to be the most sensitive parameter to process variation. Gate leakage current has been analyzed for both poly-Si gates and gates with the work function of 4.35 eV. For poly-Si gates, the gate leakage is found to influence the subthreshold swing below or at a gate oxide thickness of 1 nm. Device performance has also been analyzed at ldquoslow processrdquo corner to estimate the worst case degradation in performance matrices of the considered nano-FinFET.

Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Localization of Gate Bias Induced Threshold Voltage Degradation in a-Si:H TFTs

Abstract: This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage(Vth) degradation occurs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent Vth shift mechanism. Based on the observations, a charge-based expression for Vth shift is derived.

Current detector circuit and current mode switching regulator

Abstract: A current detector circuit detects a current supplied to a load and generates as a detection result a voltage corresponding to the detected current. A first p-channel transistor has a source connected to a power supply and a gate connected to a ground, and is configured to allow the passage therethrough of a current that is 1/N of a current flowing through a transistor which drives the load. A second p-channel transistor has a source connected to a drain of the first p-channel transistor, and a third p-channel transistor is connected to the load. A voltage mirror circuit has first and second terminals connected to respective drains of the second and third p-channel transistors. A n-channel transistor has a drain connected to the drain of the first p-channel transistor and outputs a source voltage as the detection result of the current detector circuit.

Tunnel field-effect transistor with metal source

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first conductivity type. A second source/drain region is on an opposite side of the channel region than the first source/drain region, wherein the second source/drain region is a metal region. A pocket region of a second conductivity type opposite the first conductivity type is horizontally between the channel region and the second source/drain region.

Thin film transistor (TFT) and flat panel display including the TFT and their methods of manufacture

Abstract: A Thin Film Transistor (TFT) reduces interconnection resistance of source/drain electrodes, prevents contamination from an active layer, reduces contact resistance between a pixel electrode and the source/drain electrodes, smoothly supplies hydrogen to the active layer and has high mobility, on-current characteristics, and threshold voltage characteristics The TFT includes an active layer having a channel region and source/drain regions, a gate electrode supplying a signal to the channel region, source/drain electrodes respectively connected to the source/drain regions and including at least one of Ti, a Ti alloy, Ta, and a Ta alloy; and an insulating layer interposed between the source/drain electrodes and the active layer and including silicon nitride