Showing papers on "Electronic circuit simulation published in 2010"

Circuit Simulation

Abstract: A Definitive text on developing circuit simulators Circuit Simulation gives a clear description of the numerical techniques and algorithms that are part of modern circuit simulators, with a focus on the most commonly used simulation modes: DC analysis and transient analysis. Tested in a graduate course on circuit simulation at the University of Toronto, this unique text provides the reader with sufficient detail and mathematical rigor to write his/her own basic circuit simulator. There is detailed coverage throughout of the mathematical and numerical techniques that are the basis for the various simulation topics, which facilitates a complete understanding of practical simulation techniques. In addition, Circuit Simulation: Explores a number of modern techniques from numerical analysis that are not synthesized anywhere else Covers network equation formulation in detail, with an emphasis on modified nodal analysis Gives a comprehensive treatment of the most relevant aspects of linear and nonlinear system solution techniques States all theorems without proof in order to maintain the focus on the end-goal of providing coverage of practical simulation methods Provides ample references for further study Enables newcomers to circuit simulation to understand the material in a concrete and holistic manner With problem sets and computer projects at the end of every chapter, Circuit Simulation is ideally suited for a graduate course on this topic. It is also a practical reference for design engineers and computer-aided design practitioners, as well as researchers and developers in both industry and academia.

Signal/Power Integrity Analysis for Multilayer Printed Circuit Boards Using Cascaded S-Parameters

Abstract: A cascaded S-parameter method is proposed in this paper for signal/power integrity analysis of multiple vias in a multilayer printed circuit board (PCB). The proposed method enables efficient and accurate construction and simulation of physics-based via model for complex multilayer PCB structures involving vias. The physics-based via model describes the parasitic effects near each via region as well as mutual coupling among different vias. In this model, each via portion between two parallel plates is regarded as a three-port network with two coaxial ports and one radial port between the two plates. A procedure is first developed to obtain the S-parameters of a single plate pair, which combine the three-port via networks with the impedance matrix of the parallel-plate pair. Once the S-parameters of each plate pair are obtained, an assembling technique for cascading microwave networks is further developed. The method proposed in this paper has been validated by both simulations with a commercial circuit simulator and measurements.

Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters

Abstract: We propose a technique that enables the study of weak loop filter nonlinearities in a class of continuous-time delta-sigma modulators. The technique can easily be implemented in a tool intended to simulate discrete-time modulators with linear loop filters, thereby significantly reducing the simulation time. Thanks to this technique, the utility of the Schreier Delta-Sigma toolbox can be extended to include weakly nonlinear effects in the loop filter, thus enabling the architectural exploration of alternate loop filter and operational amplifier (opamp) topologies. The results from the use of our technique are compared to those obtained using a circuit simulator, and good agreement is seen.

Analytical compact modeling of GMR based current sensors: Application to power measurement at the IC level

Abstract: An analytical compact model for giant magnetoresistance (GMR) based current sensors has been developed. Different spin-valve based full Wheatstone bridge sensors, with the current straps integrated in the chip, have been considered. These devices have been experimentally characterized in order to extract the model parameters. In this respect, we have focused on the sensors linear operation regime. The model, which allows the individual description of the magnetoresistive elements, has been implemented in a circuit simulator by means of a behavioral description language: Verilog-A. We also propose the use of the devices in a direct power measurement application at the integrated circuit (IC) level, by taking advantage of their multiplicative properties. A simple circuit is suggested, and analyzed in depth by means of the tested model, showing promising results regarding the application range.

Energy Efficient and Process Tolerant Full Adder Design in Near Threshold Region Using FinFET

Abstract: This paper investigates a robust 1-bit static full adder using FinFET at near-threshold region (NTR), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region provides minimum-energy point for the different frequency of operation with more favorable performance and variability characteristics. The proposed design features higher computing speed (by 4.49 x) and lower energy (by 3.90 x) at the expense of 1.13 x higher power dissipation. The proposed design also offers 1.38A— improvements in power variability, 2.19A— improvements in delay variability and 2.41A— improvement in power delay product (PDP) variability against process, voltage, and temperature (PVT) variations. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).

Improving verification coverage of analog circuit blocks by state space-guided transient simulation

Abstract: In this contribution a novel methodology for verification of analog circuit blocks with the aim of full coverage of the analog state space is proposed On a discretized state space model of the analog system, an efficient state space-guided input stimuli generation algorithm produces piecewise linear input stimuli for every input of the system under verification Processed by a conventional transient circuit simulator, the simulation results are covering the system's complete dynamic behavior Simulation by complete state space-covering input stimuli guarantees the verification results to be sound for every possible state and input stimulus of the circuit under verification, which increases the significance of property verification and equivalence checking of transistor netlists versus behavioral models The application to example circuits shows the feasibility of the approach

Reconfigurable Special Test Circuit of physics-based IGBT models parameter extraction

Abstract: Physics-based models of power electronic devices are the most accurate for circuit simulation purposes. However, many parameters of such models are related to device physics and structure and are not directly available for the user. The IGBT is still the most used power semiconductor device for applications at medium power and frequency ranges, due to its good compromise between on-state loss, switching loss, and ease of control. This paper presents a procedure for extracting the most important parameters of the IGBT, with physical background and electrical measurements. The goal is to develop a deeply understanding of the device-structure and to simulate correctly both steady-state and transient period with any circuit simulation software without the IGBT model provided by the manufacturer. The method consists of seven test setups and seven algorithms for extracting 13 physical and structural parameters needed in most physics-based IGBT models; by using only one Reconfigurable Special Test Circuit in order to achieve the different test setups conditions.

Accurate modeling of voltage and current waveforms with saturation and power losses in a ferrite core via two-dimensional finite elements and a circuit simulator

Abstract: This paper presents a new dynamic model of equivalent circuit to simulate in the time-domain the effects of saturation and power losses in a nonlinear magnetic component. The parameters of the model are a nonlinear inductance and a nonlinear loss resistance that are computed via two-dimensional finite elements. The effectiveness of the model is analyzed in the case of a soft ferrite inductor excited by a sinusoidal voltage source at frequencies of 500 Hz and 40 kHz. The resulting voltage and current waveforms of the inductor taken in the laboratory are then compared with those computed via the PSIM circuit simulator. PSIM is a simulation software designed for power electronics, motor control, and dynamic system simulation.

Double Gate MOSFET Modeling Based on Adaptive Neuro-Fuzzy Inference System for Nanoscale Circuit Simulation

Abstract: As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, quantum mechanical effects are expected to become more and more important. Accurate quantum transport simulators are required to explore the essential device physics as a design aid. However, because of the complexity of the analysis, it has been necessary to simulate the quantum mechanical model with high speed and accuracy. In this paper, the modeling of double gate MOSFET based on an adaptive neuro-fuzzy inference system (ANFIS) is presented. The ANFIS model reduces the computational time while keeping the accuracy of physics-based models, like non-equilibrium Green’s function formalism. Finally, we import the ANFIS model into the circuit simulator software as a subcircuit. The results show that the compact model based on ANFIS is an efficient tool for the simulation of nanoscale circuits.

Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32nm Technology

Abstract: Optimization of power and speed is a very important issue in low-voltage and low-power applications. In this paper, a 1-bit full adder cell has been successfully analyzed by assigning high-threshold voltage to some transistors and low-threshold voltage to others. Moreover, a robust full adder circuit using dual threshold voltage MOSFETs (DT-MOS) has been proposed. The proposed design features lower power dissipation (by 0.11%), higher computing speed (by 4.23%) and lower energy (power delay product) (by 4.33%). The proposed design also offers 4.2% improvement in delay variability and 3.7% improvement in PDP variability at the expense of 2.5% reduction in power variability against process, voltage, and temperature (PVT) variation. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).

Design of a wideband bandpass filter using microstrip parallel-coupled dual-mode ring resonator

Abstract: In this paper, a micostrip parallel-coupled dual-mode ring resonator is analyzed based on its equivalent transmission line circuit and the even- and odd-mode method. Closed-form formulas relating the transmission zeros and 3dB fractional bandwidth of the resonator to the circuit parameters are derived, and are verified effective by using a circuit simulator and an electromagnetic simulator. A bandpass filter is designed by using this type of dual-mode resonator, and it shows a wide passband with a 3dB fractional bandwidth of 30%, low reflection loss in the passband, and very sharp passband skirt property.

A Physics-Based Device Model of Transient Neutron Damage in Bipolar Junction Transistors

Abstract: For the purpose of simulating the effects of neutron radiation damage on bipolar circuit performance, a bipolar junction transistor (BJT) compact model incorporating displacement damage effects and rapid annealing has been developed. A physics-based approach is used to model displacement damage effects, and this modeling approach is implemented as an augmentation to the Gummel-Poon BJT model. The model is presented and implemented in the Xyce circuit simulator, and is shown to agree well with experiments and TCAD simulation, and is shown to be superior to a previous compact modeling approach.

Analysis of wave propagation in Time Domain Reflectometry circuit simulation model

Abstract: Time Domain Reflectometry (TDR) has been commonly used for testing and diagnosis of faults along a transmission line. It involves the sending of an electrical pulse along a cable and using an oscilloscope to observe the reflected pulses. In this paper, the experimental set up based on Time Domain Reflectometry technique is developed using PSpice circuit simulation software. From the PSpice circuit simulation, the incident and reflected pulses at various nodes are obtained. In order to determine the wave propagation in a Test cable, the actual reflected pulse from the Test cable need to be evaluated. However, in practice the actual reflected pulses cannot be obtained directly from the Test cable but must be measured from the oscilloscope. Therefore, in this paper, the relationship between the actual reflected pulses from the Test cable to the reflected pulses measured from an oscilloscope is established by using the electrical circuit analysis and transmission line theory. Moreover, the characteristic impedance of the Test cable can be computed accurately from this relationship.

Circuit simulation for Nano-Electro-Mechanical switches VLSI circuits

Abstract: To accurately simulate the behavior of Nano-Electro- Mechanical Switch (NEM) circuits, a NEM circuit simulation model that faithfully reproduces the NEMS device characteristics in a circuit simulation environment is needed. In this paper, we present an accurate NEMS circuit simulation model. The model is based on the 3D Finite Element Analysis (FEA) physical device that captures the device multiphysics phenomena. The NEMS circuit simulation model reproduces the same characteristics of the 3D FEA model using circuit simulation techniques. In this way, the 3D FEA physical device model is used to derive and calibrate the NEMS circuit simulation model. To evaluate the accuracy of the model, the model is implemented in a circuit simulator. The NEM circuit simulator enables the evaluation of NEMS circuit with the same accuracy of the 3D FEA physical device model at much lower cost in terms of CPU time and memory requirement. In this paper, we present an accurate NEMS circuit model derivation and a NEMS circuit simulator. The simulator is able to simulate larger NEMS circuits with the same accuracy as the FEA at an acceptable CPU time and memory requirement.

Modeling Nonquasi-Static Effects in SiGe HBTs

Abstract: The shortcomings of quasi-static and partitioned charge-based models are quantitatively demonstrated for 1-D SiGe heterojunction bipolar transistors. This points out the need to include higher order frequency-dependent terms, i.e., nonquasi-static effects in the model. Three different implementation-suitable modeling approaches are presented with associated formulations. Detailed comparison with the original theory is carried out to show the different levels of achievable accuracy of the formulated models. Circuit simulator implementations, parameter extractions, and validations of the models with device simulation results are also carried out. Frequency- and time-domain small-signal modeling results are found to be consistent and provide a high level of accuracy. For two selected cases among the various modeling approaches, results of large-signal transient switching are presented, showing excellent agreement with device simulation.

Model order reduction and sensitivity analysis

Abstract: The electronics industry provides the core technology for numerous industrial innovations. Progress in the area of microelectronics is highlighted by several milestones in chip technology, for example microprocessors and memory chips. The ongoing increase in performance and memory density would not have been possible without the extensive use of computer simulation techniques, especially electronic circuit simulation. The basis of the latter is formed by a sound framework of methods from the area of numerical methods. In recent years, the demands on the capabilities of circuit simulation have become even more stringent. Circuit simulators have become the core of all simulations within the electronics industry. Crosstalk effects in interconnect structures are modeled by large extracted RLC networks. Also, substrate effects that start playing a crucial role in determining the performance are modeled by extracting, again, large resistive or RC networks. New algorithms are needed to cope with such situations that are extremely crucial for designers. The complexity caused by these parasitic extractions must be reduced to facilitate the simulation of the circuit while preserving accuracy. Fortunately, highly accurate parasitic extraction is not necessary for all parts of the design. Each layout contains critical blocks or paths whose timing and performance is crucial for the overall functionality of the chip. High precision interconnect modeling must be used for these circuit parts to verify the functionality of the design. On the other hand, there is interconnect outside of critical paths which adds to the complexity but whose exact model is not necessary and can be simplified. For the critical paths a so-called sensitivity analysis can bring a major achievement in speed-up, by automatically determining the critical parasitic elements that provide the most dominant influence. Another important aspect is the fact that there is an increasing deviation between design and manufacturing. Due to the ever decreasing feature sizes in modern chips, deviations from the intended dimensions are becoming more probable. Designers need to cope with this, and design the circuits in such a way that a deviation from intended dimensions does not alter the functionality of the circuit. In order to investigate this properly, one needs to assume that all components can possibly be slightly different after manufacturing.The effects this has on the performance of the circuit can be studied by introducing many thousands or even millions of parameters, describing the deviations, and performing a sensitivity analysis of the circuit w.r.t. parameter changes. The aforementioned problems form the inspiration for the study in this thesis. Sensitivity analysis is crucial for the correctness of virtual design environments based on electronic circuit simulators, and gives designers insight in how to alter the designs in order to guarantee more robustness with respect to variability in the design. The problem is that a thorough sensitivity analysis requires derivatives of the solution with respect to a large amount of parameters. This is not feasible using classical methods, being far too time-consuming for modern circuits. Recently proposed methods using the adjoint problem to calculate sensitivities are far more efficient, and these form the basis for our methodology. Our work has concentrated on making such methods even more efficient, by mixing them with concepts from the area of model order reduction. This leads to very efficient, robust and accurate methods for sensitivity analysis, even if the underlying circuit is large and the number of parameters is excessive.

A novel power line communication technique based on power electronics circuit topology

Abstract: This paper presents a novel method of designing power line communication circuits, which consolidate power and data in a single bus. This method is based on power electronics topology and can derive new application circuits. The principle of the Buck-type powered-bus circuit is introduced. Taking into account the effect of transmission line, the steady-state characteristics of the circuit as well as dynamic switching characteristics are analyzed. The effectiveness of this method is verified by experimental result.

A new modified nodal analysis for nano-scale memristor circuit simulation

Abstract: It is unclear how to include the newly discovered memristor together with traditional electronic devices into a circuit simulator such as SPICE. To perform a fast prototyping of circuits composed of memristors at nano-scale, this paper introduces a new modified nodal analysis (MNA) to include this fourth circuit element into a first-order differential-algebra-equation (DAE). In the new MNA, magnetic flux is employed as the state variable for a flux-controlled memristor, called memductor. The new MNA is implemented in a circuit simulator to efficiently provide time-domain transient simulations for a number of nano-scale memristor-based circuits.

Analytic 1-D $pn$ Junction Diode Photocurrent Solutions Following Ionizing Radiation and Including Time-Dependent Changes in the Carrier Lifetime From a Nonconcurrent Neutron Pulse

Abstract: Circuit simulation codes, such as SPICE, are invaluable in the development and design of electronic circuits in radiation environments. These codes are often employed to study the effect of many thousands of devices under transient current conditions. Device-scale simulation codes are commonly used in the design of individual semiconductor components, but computational requirements limit their use to small-scale circuits. Analytic solutions to the ambipolar diffusion equation, an approximation to the carrier transport equations, may be used to characterize the transient currents at nodes within a circuit simulator. We present new analytic transient excess carrier density and photocurrent solutions to the ambipolar diffusion equation for 1-D abrupt-junction pn diodes. These solutions incorporate low-level radiation pulses and take into account a finite device geometry, ohmic fields outside the depleted region, and an arbitrary change in the carrier lifetime due to neutron irradiation or other effects. The solutions are specifically evaluated for the case of an abrupt change in the carrier lifetime during or after, a step, square, or piecewise linear radiation pulse. Noting slow convergence of the Fourier series solutions for some parameters sets, we evaluate portions of the solutions using closed-form formulas, which result in a two order of magnitude increase in computational efficiency.

High speed fully differential second generation current conveyor

Abstract: In this paper, a high speed fully differential second generation current conveyor (FDCCII+) is presented The proposed FDCCII+ is based on using fully differential buffer [1] and class AB push-pull output stage with a new standby current control circuitry The circuit is realized using 90nm CMOS TSMC technology model under 12V single supply voltage The proposed realization of FDCCII+ input differential voltage dynamic range is from −045V to 045V The total power dissipation of the circuit is 17mW The simulated bandwidth of the FDCCII+ is 254MHz under 10KΩ load at X and Z terminals All the circuit simulations are done using Cadence Virtuoso SPECTRE circuit simulator

Closed-Form Expressions for the Equivalent Circuit Model of Square-Waveguide T-Junctions and Its Application in Ortho-Mode Transducer Design

Abstract: In this paper, closed-form expressions for the equivalent circuit model of square-waveguide T-junctions are presented. The square-waveguide T-junction is first modeled as a generalized admittance matrix and then reduced to a general five-port network. It is theoretically seen that the general five-port network can be simplified as a combination of a two-port subnetwork and a three-port subnetwork through the mode-matching analysis. Accurate closed-form expressions are derived with proper approximations to calculated the admittance parameters of these two subnetworks. A short-circuited branch ortho-mode transducer is then designed in a circuit simulator using the proposed equivalent circuit model. Measured results exhibit an excellent agreement with those from circuit simulation.

Modeling the inter-electrode capacitances of Si CoolMOS transistors for circuit simulation of high efficiency power systems

Abstract: The CoolMOS™+ transistor is a power MOSFET type device that utilizes a “super-junction” embedded within its drift region in order to improve the trade-off between on-resistance and breakdown voltage. The super-junction results in unique inter-electrode capacitance characteristics that require an advanced modeling approach to accurately represent switching performance. This paper describes a new compact circuit simulator model for the CoolMOS™ transistor and demonstrates the model performance using the Saber† simulator for a 650 V, 60 A device. The model is suitable for implementation in the Saber simulator that accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. Simulation results show excellent agreement with measurement results in contrast to previous modeling approaches used for this device. The compact model developed in this work is going to be utilized in the design of a high efficiency soft-switching inverter for electric vehicle motor drives and a high efficiency bidirectional DC-DC converter at zero-voltage switching (ZVS) operation.

Adaptive Content-aware Aging Simulations

Abstract: A system and method for simulating aging parameters of a System-on-Chip (SoC) integrated circuit is disclosed. A SoC integrated circuit is first divided into a plurality of blocks in accordance with the nature or the operating conditions of each block. The simulation of a digital circuit based block is performed by a static timing analyzer. The simulation of a mixed signal based block is performed by first employing a fresh device model to obtain relevant operation conditions, such as node voltages. Based upon the operation conditions and reliability characterization data, parameters degradation calculators assess aging characteristic factors of each block. In a subsequent simulation, a circuit simulator calculates the design corners of a SoC chip based upon the characteristic factors of each block.

Surrogate Modeling of Low Noise Amplifiers Based on Transistor Level Simulations

Abstract: Although the behavior of several RF circuit blocks can be accurately evaluated via transistor-level simulations, the design space exploration is limited by the high computational cost of such simulations. Therefore, cheap-to-evaluate surrogate models of the circuit simulator are introduced. This paper presents some results of a feasibility study concerning the development of surrogate models of low noise amplifiers.

Educational reconfigurable platform for courses on power electronics

Abstract: Power electronics applications have become ubiquitous among electronic products today. As a consequence, a great increase on the demand of professionals by the industry has been observed. This has a direct consequence on the electrical and electronics engineering curricula, as they have to meet the requirements of an industry with an increasing number of products requiring power electronics solutions. Power electronics teaching is usually divided into three areas, as well as it is in other electronics knowledge areas: lecture-based sessions, circuit simulation sessions and practical training. The aim of this paper is to propose a specific tool for the practical training sessions. It is based on a reconfigurable educational platform which allows a fast experimentation with different power converter topologies. The proposed approach presents an improved hands-on training, which allows the student reinforcing theoretical concepts while facing some practical aspects as measurements techniques and safety issues.

Compact model and circuit simulations for asymmetric, independent gate FinFETs

Abstract: We present a rigorous surface-potential-based compact model of independent-gate asymmetric FinFETs enabled by solving several long-standing theoretical problems. The model is verified with TCAD simulations and is implemented in a standard circuit simulator. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric FinFETs.

Finite difference based vibration simulation analysis of a segmented distributed piezoelectric structronic plate system

Abstract: Electrical modeling of piezoelectric structronic systems by analog circuits has the disadvantages of huge circuit structure and low precision. However, studies of electrical simulation of segmented distributed piezoelectric structronic plate systems (PSPSs) by using output voltage signals of high-speed digital circuits to evaluate the real-time dynamic displacements are scarce in the literature. Therefore, an equivalent dynamic model based on the finite difference method (FDM) is presented to simulate the actual physical model of the segmented distributed PSPS with simply supported boundary conditions. By means of the FDM, the four-ordered dynamic partial differential equations (PDEs) of the main structure/segmented distributed sensor signals/control moments of the segmented distributed actuator of the PSPS are transformed to finite difference equations. A dynamics matrix model based on the Newmark-β integration method is established. The output voltage signal characteristics of the lower modes (m ≤ 3, n ≤ 3) with different finite difference mesh dimensions and different integration time steps are analyzed by digital signal processing (DSP) circuit simulation software. The control effects of segmented distributed actuators with different effective areas are consistent with the results of the analytical model in relevant references. Therefore, the method of digital simulation for vibration analysis of segmented distributed PSPSs presented in this paper can provide a reference for further research into the electrical simulation of PSPSs.

Grid-Enabled Parallel Simulation Based on Parallel Equation Formulation

Abstract: Parallel simulation is an efficient way to cope with long runtimes and high computational requirements in simulations of modern complex integrated electronic circuits and systems. This paper presents an algorithm for parallel simulation based on parallelization in equation formulation and simultaneous calculation of matrix contributions for nonlinear analog elements. In addition, the paper describes the development of a grid interface for a parallel simulator that enables a designer to perform simulations on distant computer clusters. Performances of the developed parallel simulation algorithm are evaluated by simulation of a microelectromechanical system.

Automated parameter extraction software for silicon and high-voltage silicon carbide power diodes

Abstract: This paper presents an automated parameter extraction software package developed for constructing silicon (Si) and silicon carbide (SiC) power diode models, which is called DIode Model Parameter extrACtion Tools (DIMPACT). This software tool extracts the data necessary to establish a library of power diode component models and provides a method for quantitatively comparing between different types of devices and establishing performance metrics for device development. To verify the accuracy of DIMPACT, the extracted model parameter sets are incorporated into the circuit simulation software to compare model predictions with measured static and transient diode characteristics. In this paper, the DIMPACT parameter extraction results are demonstrated for a 45 V, 15 A Si Schottky diode; a 600 V, 200 A Si PiN diode; a 10 kV, 5 A SiC Junction Barrier Schottky (JBS) diode; and a 10 kV, 20 A SiC PiN diode. The validation results indicate that the model parameters extracted using DIMPACT are accurate.