Showing papers on "Equivalent series resistance published in 2009"

Transformerless DC–DC Converters With High Step-Up Voltage Gain

Abstract: Conventional dc-dc boost converters are unable to provide high step-up voltage gains due to the effect of power switches, rectifier diodes, and the equivalent series resistance of inductors and capacitors. This paper proposes transformerless dc-dc converters to achieve high step-up voltage gain without an extremely high duty ratio. In the proposed converters, two inductors with the same level of inductance are charged in parallel during the switch-on period and are discharged in series during the switch-off period. The structures of the proposed converters are very simple. Only one power stage is used. Moreover, the steady-state analyses of voltage gains and boundary operating conditions are discussed in detail. Finally, a prototype circuit is implemented in the laboratory to verify the performance.

Enhancement mechanism of electrochemical capacitance in nitrogen-boron-doped carbons with uniform straight nanochannels

Abstract: Anodic aluminum oxide (AAO) with uniform straight nanochannels was completely coated with pure, N-doped, or B-doped carbon layer. Their electric double layer capacitances are measured in aqueous (1 M sulfuric acid) and organic (1 M Et4NBF4/polypropylene carbonate) electrolyte solutions in order to investigate the capacitance enhancement mechanisms caused by N- or B-doping. Since the three types of carbon-coated AAOs (pure, N-doped, or B-doped) have exactly the same pore structure, the observed capacitance enhancement was ascribable to only the following factors: (i) better wettability, (ii) the decrease of equivalent series resistance, (iii) the contribution of space-charge-layer capacitance, and (iv) the occurrence of pseudocapacitance. From the measurements of the wettability and the electrical resistance of the coated AAOs together with the electrochemical investigation (the cyclic voltammetry, the galvanostatic charge/discharge cycling, and the impedance analysis), it is concluded that the pseudocapac...

Area-scaling of organic solar cells

Abstract: We report on the performance of organic solar cells based on pentacene/C60 heterojunctions as a function of active area. Devices with areas of 0.13 and 7 cm2 were fabricated on indium-tin-oxide (ITO) coated glass. Degradation of the performance with increased area is observed and analyzed in terms of the power loss density concept. The various power loss contributions to the total series resistance (RSA) are measured independently and compared to the values of the series resistance extracted from the current-voltage characteristics using a Shockley equivalent circuit model. The limited sheet resistance of ITO is found to be one of the major limiting factors when the area of the cell is increased. To reduce the effects of series resistance, thick, electroplated, metal grid electrodes were integrated with ITO in large-area cells. The metal grids were fabricated directly onto ITO and passivated with an insulator to prevent electrical shorts during the deposition of the top Al electrode. By integrating metal ...

A Simple Offline Technique for Evaluating the Condition of Aluminum–Electrolytic–Capacitors

Abstract: This paper presents a very simple technique to estimate the condition of aluminum-electrolytic-capacitors. The aging of aluminum-electrolytic-capacitors is expressed by the increase of their equivalent series resistance (ESR) and the reduction of their capacitance. Thus, the proposed technique is based on the estimation of both the ESR and capacitance values. To implement the proposed technique, the capacitor is fed by a sinusoidal voltage with the required power. The resultant impedance vector defined by the capacitor voltage and current gives enough information to estimate the condition of the capacitor.

Fast series resistance imaging for silicon solar cells using electroluminescence

Abstract: We introduce a fast and easy to apply method for determining the local series resistance of standard silicon solar cells. For this method only two electroluminescence images taken at different voltages are needed. From these two images, the local voltage and the local current density through the device can be calculated. Knowing these parameters for each pixel yields the local series resistance. By calculating the cell's dark saturation current from the lower voltage image, the method also works with multicrystalline material. We show images, acquired in only 300 ms and compare them with other luminescence based series resistance images. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Enhanced lateral current transport via the front N+ diffused layer of n‐type high‐efficiency back‐junction back‐contact silicon solar cells

Abstract: N-type back-contact back-junction solar cells were processed with the use of industrially relevant structuring technologies such as screen-printing and laser processing. Application of the low-cost structuring technologies in the processing of the high-efficiency back-contact back-junction silicon solar cells results in a drastic increase of the pitch on the rear cell side. The pitch in the range of millimetres leads to a significant increase of the lateral base resistance. The application of a phosphorus doped front surface field (FSF) significantly reduces the lateral base resistance losses. This additional function of the phosphorus doped FSF in reducing the lateral resistance losses was investigated experimentally and by two-dimensional device simulations. Enhanced lateral majority carrier's current transport in the front n+ diffused layer is a function of the pitch and the base resistivity. Experimental data show that the application of a FSF reduces the total series resistance of the measured cells with 3.5 mm pitch by 0.1 Ω cm2 for the 1 Ω cm base resistivity and 1.3 Ω cm2 for the 8 Ω cm base resistivity. Two-dimensional simulations of the electron current transport show that the electron current density in the front n+ diffused layer is around two orders of magnitude higher than in the base of the solar cell. The best efficiency of 21.3% was obtained for the solar cell with a 1 Ω cm specific base resistivity and a front surface field with sheet resistance of 148 Ω/sq. Copyright © 2008 John Wiley & Sons, Ltd.

Analysis of temperature dependence of dark current mechanisms for long-wavelength HgCdTe photovoltaic infrared detectors

Abstract: Resistance-voltage curves of n-on-p Hg1−хCdxTe long-wavelength infrared photodiodes forming 128-element array are measured in the temperature range of 40–150 K. Experimentally obtained characteristics are fitted by the simultaneous-mode nonlinear fitting program. The dark current mechanisms induced by diffusion, generation recombination, trap-assisted tunneling, band-to-band tunneling, and series resistance effect are included in the physical model for R-V curve fitting. Six characteristic parameters as function of temperature are extracted from measured R-V curves. The characteristics of extracted current components at low temperatures indicate significant contributions from tunneling effects, which is the dominant leakage current mechanism for reverse bias greater than approximately 50 mV. The Hg-vacancy-induced acceptor trap tends to invert to donor type at higher temperature, typically larger than 120 K, while it can maintain stable at the temperature of 60–40 K. The stable temperature of ion-implanta...

Materials, Devices, and Circuits of Transparent Amorphous-Oxide Semiconductor

Abstract: This paper presents the following recent investigations of transparent amorphous-oxide semiconductors (TAOS) from materials to devices and circuits. 1) Composition of metals in TAOS are widely explored with the aim of seeking semiconductors suitable for the channel layers of thin-film transistors (TFTs) composing backplanes for flat-panel displays. It is found in combinatorial approaches to the materials exploration that indium-based ternary TAOS (In-X-O) and their TFTs show the properties and the performance as good as those of the most popular material of amorphous In-Ga-Zn-O (alpha-IGZO) when X = Zn or Ge. 2) Defects and impurities in TAOS are investigated by theoretical approaches. The first-principle calculation of the electron states reveals that charge-neutral oxygen vacancy or interstitial forms the density of states around mid-gap level and does not generate carriers directly, while hydrogen impurity raises the Fermi level beyond the conduction-band minimum and acts as a donor in TAOS. 3) Device structures of TAOS-TFTs are also investigated extensively for better performance and stability. It is found in channel-etch type TFTs with bottom-gate inverse-stagger structures that the TFT characteristics and stability are significantly improved by chemically removing the back-channel layer in a wet-etching process. Coplanar homojunction (CH) structure is proposed as a novel device structure where conductive alpha-IGZO regions work as the source and drain electrodes to the channel region of semiconductor alpha-IGZO. The CH TFTs show excellent characteristics and stability, with low series resistance without any difficulty in making good electrical contact between metals and TAOS. 4) Circuits using TAOS-TFTs are demonstrated. A ring oscillator composed of fifteen-stage inverters with a buffer circuit operates as designed by circuit simulation with a TFT model for hydrogenated amorphous Si TFTs. Pixel circuits composed of three TFTs and one transparent capacitor successfully drive organic light-emission diode cells without a planarization layer on a 2-in diagonal panel having 176 times144 times 3 pixels.

A New Technique to Extract the Source/Drain Series Resistance of MOSFETs

Abstract: This letter demonstrates a new technique to extract the source/drain series resistance of MOSFETs. Unlike the well-known total resistance techniques, Rsd is extracted in a way that the result is insensitive to effective length and mobility variations. The technique has been successfully applied to 45-nm bulk and fully depleted SOI MOSFETs with high-κ and metal gate, having channel length down to 22 nm. The technique provides a high accuracy and allows fast measurements and statistical analysis.

Impedance Characteristics and Parasitic Speed Limitations of High-Speed 850-nm VCSELs

Abstract: The impedance characteristics of high-speed oxide-confined 850-nm vertical-cavity surface-emitting lasers have been studied with the aim of identifying the importance of device parasitics for the modulation bandwidth. Through equivalent circuit modeling, it is confirmed that device parasitics have a major impact on the bandwidth and the importance of each individual circuit element has been investigated. According to the extrapolation of the parameters derived from S11 measurements below 20 GHz towards higher frequencies and assuming that the mesa capacitance can be reduced by adding a few extra oxide layers without significantly affecting series resistance, our model predicts that the 3-dB parasitic frequency can be increased from 22 to above 30 GHz. Accounting also for bandwidth limitations due to thermal effects, we expect an increase of the modulation bandwidth of several gigahertz which may enable direct current modulation at 40 Gb/s.

Impedance spectroscopy of thin-film CdTe/CdS solar cells under varied illumination

Abstract: The electrical properties of CdTe/CdS solar cells grown by metal organic chemical vapor deposition were investigated by a technique of impedance measurements under varied intensity of AM1.5 illumination. A generalized impedance model was developed and applied to a series of CdTe/CdS cells with variations in structure and doping. The light measurements were compared to the conventional ac measurements in dark under varied dc bias, using the same methodology for equivalent circuit analysis in both cases. Detailed information on the properties of the device structure was obtained, including the properties of the main p-n junction under light, minority carrier lifetime, back contact, as well as the effect of the blocking ZnO layer incorporated between the transparent conductor and CdS layers. In particular, the comparison between samples with different chemical concentrations of As has shown that the total device impedance and the series resistance are strongly increased at lower As densities, resulting in the lower collection current and efficiencies. At the same time the minority carrier lifetime was found to be one order of magnitude larger for the lowest value of As density, when compared to the optimized devices.

Calculation of the Capacitances of Conductors -- Perspectives for the Optimization of Electronic Devices

Abstract: The equation describing the capacitance of capacitors is determined. It is shown that by optimizing the material of the conducting electrodes, the capacitance of capacitors reaching the quantum regime can be substantially enhanced or reduced. Dielectric capacitors with negative total capacitances are suggested and their properties analyzed. Resulting perspectives to enhance the performance of electronic devices are discussed.

Mobility extraction in SOI MOSFETs with sub 1 nm body thickness

Abstract: In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem. Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.

Quadratic differential and integration technique in V 2 control buck converter with small ESR capacitor

Abstract: This paper proposes a quadratic differential and integration (QDI) technique for the design of buck converters with small equivalent series resistance (ESR) of the output capacitor. The QDI circuit not only further removes the dependence of ESR in the V2 control but also achieves a fast transient response with small load transient voltage variation. The experimental results show the output voltage can have voltage ripple about 30 mV and recovery time of 20 μs in case of 300 mA load current variation.

Method for production of electrolyte capacitors

Abstract: The invention relates to a process for producing electrolytic capacitors with low equivalent series resistance, to electrolytic capacitors produced by this process and to the use of such electrolytic capacitors.

Design of an “all solid-state” supercapacitor based on phosphoric acid doped polybenzimidazole (PBI) electrolyte

Abstract: The effectiveness of phosphoric acid doped polybenzimidazole as a polymer electrolyte membrane to fabricate an all solid-state super capacitor has been explored using hydrous RuO2/carbon composite electrodes (20 wt.%) of surface area 250 m2 g−1 with many intrinsic advantages. The electrochemical evaluation of these super capacitors through cyclic voltammetry, charge/discharge and impedance measurements demonstrate the utility of this type of thin, compact and flexible supercapacitor capable of functioning at 150 °C to yield a maximum capacitance of about 290 F g−1 along with a life of more than 1,000 cycles. A power density of 300 W kg−1 and energy density of 10 Wh kg−1 have been accomplished although the equivalent series resistance (ESR) of about 3.7 Ω needs to be reduced further for high rated applications.

Influence of Mesoporous Separator Properties on the Parameters of Electrical Double-Layer Capacitor Single Cells

Abstract: The specific surface area, pore size distribution function, micropore and mesopore volume, and area values have been obtained by gas adsorption/absorption method for various separator materials prepared from polypropylene, cellulose, and poly(vinylidene fluoride). Electrical double-layer capacitors (EDLCs) based on the two identical ideally polarizable nanoporous carbide-derived carbon electrodes and different mesoporous separator materials in 1 M (C 2 H 5 ) 3 CH 3 NBF 4 acetonitrile solution have been tested by cyclic voltammetry and electrochemical impedance methods. The limits of ideal polarizability, low-frequency limiting capacitance and series resistance, time constant, complex power components, and electrolyte conductivity in the separator matrix have been obtained and discussed. The model of Srinivasan and Weidner [J. Electrochem. Soc., 146, 1650 (1999)] has been modified by introducing into it the very high-frequency constant phase and charge-transfer resistance elements. The applicability limits of the modified model have been tested. Noticeable influence of separator chemical composition, thickness, specific surface area, and pore size distribution on the characteristics of the EDLC single cells have been found.

High performance metal-insulator-metal capacitor using a SrTiO3/ZrO2 bilayer

Abstract: Future integration of metal-insulator-metal capacitors requires devices with high capacitance density and low quadratic voltage coefficient of capacitance (α). A major problem is that the increase in capacitance density is usually accompanied by increased voltage nonlinearities. By combining two high-k materials with opposite α, it is demonstrated that it is possible to obtain capacitors with both high capacitance density and minimal nonlinearity. A SrTiO3/ZrO2 bilayer was used to elaborate capacitors displaying a voltage coefficient of −60 ppm/V2 associated with a density of 11.5 fF/μm2. These devices constitute excellent candidates for the next generation of metal-insulator-metal capacitors.

Method for producing solid electrolyte capacitors

Abstract: The invention relates to a process for producing electrolyte capacitors with high capacitances and low equivalent series resistance, to electrolyte capacitors produced by this process and to the use of such electrolyte capacitors.

Performance Analysis of 60-nm Gate-Length III–V InGaAs HEMTs: Simulations Versus Experiments

Abstract: An analysis of recent experimental data for high-performance In0.7Ga0.3As high electron mobility transistors (HEMTs) for logic applications is presented. By using a fully quantum mechanical ballistic model, we simulate In0.7Ga0.3As HEMTs with gate lengths of LG = 60, 85, and 135 nm and compare the result to the measured IV characteristics, including drain-induced barrier lowering, subthreshold swing, and threshold voltage variation with gate insulator (wide-bandgap barrier layer) thickness, as well as on-current performance. To first order, devices with three different oxide thicknesses and channel lengths can all be described by a ballistic model for the channel with appropriate values of parasitic series resistance. For high gate and drain voltages ( VGS-VT=0.5 V and VDS=0.5 V), however, the ballistic simulations consistently overestimate the measured on-current (a sign of higher transconductance), and they do not show the experimentally observed decrease in on-current with increasing gate length. With no parasitic series resistance at all, the simulated on-current of the LG = 60 nm device is about twice the measured current. According to the simulation, the estimated ballistic carrier injection velocity for this device is about 2.7 times 107cm/s. Because of the importance of the semiconductor capacitance, the simulated gate capacitance is about 2.5 times less than the insulator/barrier capacitance. Possible causes of the transconductance degradation observed experimentally under high gate voltages in these devices are also explored. In addition to a possible gate-voltage-dependent scattering mechanism, the limited ability of the source to supply carriers to the channel and the effect of nonparabolicity are likely to play a role. The drop in the on-current at higher gate biases with increasing gate length, is an indication that the devices operate below the ballistic limit.

Influence of polymer solar cell geometry on series resistance and device efficiency

Abstract: In order to study the influence of the organic solar cell device layout on the photovoltaic parameters, we systematically varied its geometry. By knowledge of all sheet resistances in the device, we were able to correlate the series resistance with the geometry of the device using a simple model for its calculation. Deviations between experiment and calculation could be related with the solar cell geometry and understood by postulating curved transport ways of the current within the largely resistive ITO-layer. Thus, a further refinement of the calculation is required in order to minimize the deviation between calculation and experiment. Short solar cell lengths and ITO-bridges yield minimal series resistance and best conversion efficiency.

Solar cell with a backside via to contact the emitter layer

Abstract: A solar cell structure is provided for reducing shadow losses without increasing series resistance in the solar cell device. The solar cell device may form an electrical contact to a solar cell emitter layer from the backside of the solar cell device. With this structure, the emitter contact shadow losses may be reduced significantly while simultaneously decreasing device series resistance.

Broad output current scope low pressure difference linear manostat

Abstract: A low dropout linear voltage regulator with wide output current range and low pressure difference, comprises an error amplifier in the folding common source and common gate structure, a buffer circuit, a driving element, a feedback circuit, a load capacitance equivalent series resistance compensating circuit and a multistage Miller compensation circuit, wherein the buffer circuit changes the low frequency pole into a medium frequency pole and a high frequency pole; the large load capacitance of the load capacitance equivalent series resistance compensating circuit pushes the main pole to the low frequency, causing the gain crossover point to push inwards, and generating a medium frequency zero point for counteracting the medium frequency pole connected serially with the equivalent series resistance; the stride multilevel Miller compensation circuit generates a medium high frequency pole and a medium high frequency zero point slightly smaller than the medium high frequency pole for advancing the phase margin, thereby not only adding the unity gain bandwidth, but also saving considerable chip area When the output current has a large change range, the structure provided by the invention generates wider unity gain bandwidth, provides the phase margin of greater than 85 degrees, ensures the stability of the system and advances the low pressure difference linear voltage stabilization performance

Modeling and Analysis of Parasitic Resistance in Double-Gate FinFETs

Abstract: A comprehensive model is presented to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width. The model incorporates the contribution of spreading, sheet, and contact resistances. The spreading resistance is modeled using a standard two-dimensional (2-D) model generalized to 3-D. The contact resistance is modeled by generalizing the one-dimensional (1-D) transmission line model to 2-D and 3-D with appropriate boundary conditions. The model is compared with the S/D resistance determined from 3-D device simulations and experimental data. We show excellent agreement between our model, the simulations, and experimental data.