Showing papers on "Etching (microfabrication) published in 2008"

Silicon nanowire radial p-n junction solar cells.

Abstract: We have demonstrated a low-temperature wafer-scale etching and thin film deposition method for fabricating silicon n−p core−shell nanowire solar cells. Our devices showed efficiencies up to nearly 0.5%, limited primarily by interfacial recombination and high series resistance. Surface passivation and contact optimization will be critical to improve device performance in the future.

Graphene Oxidation: Thickness-Dependent Etching and Strong Chemical Doping

Abstract: Patterned graphene shows substantial potential for applications in future molecular-scale integrated electronics. Environmental effects are a critical issue in a single-layer material where every atom is on the surface. Especially intriguing is the variety of rich chemical interactions shown by molecular oxygen with aromatic molecules. We find that O2 etching kinetics vary strongly with the number of graphene layers in the sample. Three-layer-thick samples show etching similar to bulk natural graphite. Single-layer graphene reacts faster and shows random etch pits in contrast to natural graphite where nucleation occurs at point defects. In addition, basal plane oxygen species strongly hole dope graphene, with a Fermi level shift of ∼0.5 eV. These oxygen species desorb partially in an Ar gas flow, or under irradiation by far UV light, and readsorb again in an O2 atmosphere at room temperature. This strongly doped graphene is very different from “graphene oxide” made by mineral acid attack.

Permeable silica shell through surface-protected etching.

Abstract: We describe a "surface-protected etching" strategy that allows convenient conversion of sol-gel derived silica into porous structures. Poly(vinyl pyrrolidone) is used to protect the near surface layer, and NaOH is used to selectively etch the interior of the silica spheres. Etching initially yields porous structures and eventually removes the core to leave behind hollow silica spheres with porous shells. This strategy is useful for constructing core-shell systems where active nanomaterials are embedded in silica shell for enhanced stability against aggregation. We experimentally demonstrate use of the surface-protected etching approach to create openings on silica shells; these openings allow dissolved chemical species to reach embedded catalytic particles to be chemically transformed while the porous shells continue to act as effective barriers against aggregation and loss of activity of the core particles. We also show that, by controlling the extent of etching, it is possible to control the permeation rate of the chemical species through the shells.

Preparation of Large-Area Uniform Silicon Nanowires Arrays through Metal-Assisted Chemical Etching

Abstract: A facile fabricating method has been established for large-area uniform silicon nanowires arrays All silicon nanowires obtained were single crystals and epitaxial on the substrate Six kinds of silicon wafers with different types, surface orientations, and doping levels were utilized as starting materials With the catalysis of silver nanoparticles, room-temperature mild chemical etching was conducted in aqueous solution of hydrofluoric acid (HF) and hydrogen peroxide (H2O2) The corresponding silicon nanowires arrays with different morphologies were obtained The silicon nanowires possess the same type and same doping level of the starting wafer All nanowires on the substrate have the same orientation For instance, both (100)- and (111)-oriented p-type wafers produced silicon nanowires in the (100) direction For every kind of silicon wafer, the effect of etching conditions, such as components of etchant, temperature, and time, were systemically investigated This is an appropriate method to produce a

Broadband moth-eye antireflection coatings on silicon

Abstract: We report a bioinspired templating technique for fabricating broadband antireflection coatings that mimic antireflective moth eyes. Wafer-scale, subwavelength-structured nipple arrays are directly patterned on silicon using spin-coated silica colloidal monolayers as etching masks. The templated gratings exhibit excellent broadband antireflection properties and the normal-incidence specular reflection matches with the theoretical prediction using a rigorous coupled-wave analysis (RCWA) model. We further demonstrate that two common simulation methods, RCWA and thin-film multilayer models, generate almost identical prediction for the templated nipple arrays. This simple bottom-up technique is compatible with standard microfabrication, promising for reducing the manufacturing cost of crystalline silicon solar cells.

Silicon nanowires for rechargeable lithium-ion battery anodes

Abstract: Large-area, wafer-scale silicon nanowire arrays prepared by metal-induced chemical etching are shown as promising scalable anode materials for rechargeable lithium battery. In addition to being low cost, large area, and easy to prepare, the electroless-etched silicon nanowires (SiNWs) have good conductivity and nanometer-scale rough surfaces; both features facilitate charge transport and insertion/extraction of Li ions. The electroless-etched SiNWs anode showed larger charge capacity and longer cycling stability than the conventional planar-polished Si wafer.

Wafer-scale silicon nanopillars and nanocones by Langmuir-Blodgett assembly and etching

Abstract: We have developed a method combining Langmuir–Blodgett assembly and reactive ion etching to fabricate nanopillars with uniform coverage over an entire 4 inch wafer. We demonstrated precise control over the diameter and separation between the nanopillars ranging from 60 to 600 nm. We can also change the shape of the pillars from having vertical to tapered sidewalls with sharp tips exhibiting a radius of curvature of 5 nm. This method opens up many possible opportunities in nanoimprinting, solar cells, batteries, and scanning probes.

Methods of etching articles via microcontact printing

Abstract: Improved methods of forming a patterned self-assembled monolayer on a surface and derivative articles are provided. According to one method, an elastomeric stamp is deformed during and/or prior to using the stamp to print a self-assembled molecular monolayer on a surface. According to another method, during monolayer printing the surface is contacted with a liquid that is immiscible with the molecular monolayer-forming species to effect controlled reactive spreading of the monolayer on the surface. Methods of printing self-assembled molecular monolayers on nonplanar surfaces and derivative articles are provided, as are methods of etching surfaces patterned with self-assembled monolayers, including methods of etching silicon. Optical elements including flexible diffraction gratings, mirrors, and lenses are provided, as are methods for forming optical devices and other articles using lithographic molding. A method for controlling the shape of a liquid on the surface of an article is provided, involving applying the liquid to a self-assembled monolayer on the surface, and controlling the electrical potential of the surface.

Silicon nanowire array photoelectrochemical solar cells

Abstract: Silicon nanowires (SiNWs) arrays prepared by electroless etching show excellent optical antireflectivity over a wide spectral bandwidth from 300to1000nm and surface defect-induced electrical conductivity. Both characteristics make the SiNWs a promising material for photovoltaic cell applications. Photoelectrochemical (PEC) measurements showed the electroless etching SiNWs are remarkably photoactive and effective in enhancing photovoltaic properties including photocurrent and photovoltage. Since electroless etching can enable simple, wafer-scale fabrication of SiNWs without the need of doping. SiNWs array thus prepared show great promise as low-cost and scalable photovoltaic-type PEC materials.

Contrasting characteristics of linear-field and cross-field atmospheric plasma jets

Abstract: This letter reports an experimental study of two types of atmospheric pressure plasma jets in terms of their fundamental properties and their efficiency in etching polymeric materials. The first plasma jet has a cross-field configuration with its electric field perpendicular to its gas flow field, whereas the second is a linear-field device having parallel electric and flow fields. The linear-field jet is shown to drive electron transportation to the downstream application region, thus facilitating more active plasma chemistry there. This is responsible for its etching rate of polyamide films being 13-fold that of its cross-field counterpart.

Developments of Plasma Etching Technology for Fabricating Semiconductor Devices

Abstract: Plasma etching technologies such as reactive ion etching (RIE), isotropic etching, and ashing/plasma cleaning are the currently used booster technologies for manufacturing all silicon devices based on the scaling law. The needs-driven conversion from the wet etching process to the plasma/dry etching process is reviewed. The progress made in plasma etching technologies is described from the viewpoint of requirements for the manufacturing of devices. The critical applications of RIE, isotropic etching, and plasma ashing/cleaning to form precisely controlled profiles of high-aspect-ratio contacts (HARC), gate stacks, and shallow trench isolation (STI) in the front end of line (FEOL), and also to form precise via holes and trenches used in reliable Cu/low-k (low-dielectric-constant material) interconnects in the back end of line (BEOL) are described in detail. Some critical issues inherent to RIE processing, such as the RIE-lag effect, the notch phenomenon, and plasma-induced damage including charge-up damage are described. The basic reaction mechanisms of RIE and isotropic etching are discussed. Also, a procedure for designing the etching process, which is strongly dependent on the plasma reactor configuration, is proposed. For the more precise critical dimension (CD) control of the gate pattern for leading-edge devices, the advanced process control (APC) system is shown to be effective.

Wafer-scale patterning of sub-40 nm diameter and high aspect ratio (>50:1) silicon pillar arrays by nanoimprint and etching

Abstract: We demonstrate wide-area fabrication of sub-40 nm diameter, 1.5 µm tall, high aspect ratio silicon pillar arrays with straight sidewalls by combining nanoimprint lithography (NIL) and deep reactive ion etching (DRIE). Imprint molds were used to pre-pattern nanopillar positions precisely on a 200 nm square lattice with long range order. The conventional DRIE etching process was modified and optimized with reduced cycle times and gas flows to achieve vertical sidewalls; with such techniques the pillar sidewall roughness can be reduced below 8 nm (peak-to-peak). In some cases, sub-50 nm diameter pillars, 3 µm tall, were fabricated to achieve aspect ratios greater than 60:1.

Synthesis of silicon nanowires and nanofin arrays using interference lithography and catalytic etching.

Abstract: We report results on the synthesis of silicon nanostructures that were fabricated using a combination of interference lithography and catalytic etching. With this technique, we were able to create ...

Fabrication of low-loss photonic wires in silicon-on-insulator using hydrogen silsesquioxane electron-beam resist

Abstract: Fully etched photonic wires in silicon-on-insulator have been fabricated and propagation loss values as low as 0.92 plusmn 0.14 dB/cm have been obtained. Hydrogen silsesquioxane (HSQ) was used as an electron beam resist and as a direct mask in the dry-etch processing of the silicon core layer. The dimensional repeatability of the fabrication process was also estimated through measurements of the wavelength selection performance of nominally identical photonic wire Bragg gratings fabricated at intervals over a period of 37 days.

GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

Abstract: A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current–gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.

Solar cell and method of manufacture

Abstract: A solar cell that is readily manufactured using processing techniques which are less expensive than microelectronic circuit processing. In preferred embodiments, printing techniques are utilized in selectively forming masks for use in etching of silicon oxide and diffusing dopants and in forming metal contacts to diffused regions. In a preferred embodiment, p-doped regions and n-doped regions are alternately formed in a surface of the wafer through use of masking and etching techniques. Metal contacts are made to the p-regions and n-regions by first forming a seed layer stack that comprises a first layer such as aluminum that contacts silicon and functions as an infrared reflector, second layer such titanium tungsten that acts as diffusion barrier, and a third layer functions as a plating base. A thick conductive layer such as copper is then plated over the seed layer, and the seed layer between plated lines is removed. A front surface of the wafer is preferably textured by etching or mechanical abrasion with an IR reflection layer provided over the textured surface. A field layer can be provided in the textured surface with the combined effect being a very low surface recombination velocity.

Selective etching of silicon nitride

Abstract: Methods for etching dielectric layers comprising silicon and nitrogen are provided herein. In some embodiments, such methods may include providing a substrate having a dielectric layer comprising silicon and nitrogen disposed thereon, forming reactive species from a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) using a remote plasma; and etching the dielectric layer using the reactive species. In some embodiments, an oxide layer is disposed adjacent to the dielectric layer. In some embodiments, the flow rate ratio of the process gas can be adjusted such that an etch selectivity of the dielectric layer to at least one of the oxide layer or the substrate is between about 0.8 to about 4.

Sculpturing Effect of Chloride Ions in Shape Transformation from Triangular to Discal Silver Nanoplates

Abstract: The sculpturing effect of chloride ions on the shape transformation of silver nanoparticles is presented. UV−vis spectroscopy and transmission electron microscopy (TEM) were used to monitor the evolution of silver nanoplates. Cl− can etch the corners and side faces of the silver nanoprism, and the resulting nanoparticles are disk-like in shape. The dissolved silver atoms would aggregate to form small silver clusters, which were stabilized by the Cl− and citrate ions. The facet-selective etching effect of Cl− is mainly attributed to the surface energy difference of each face of the nanoplate. The thickness of the nanodisk increased during the etching process because of the redeposition of sliver clusters on the {111} planes. The prepared nanodisk also gave rise to high SERS intensity of the probing molecule.

Direct synthesis and properties of K2SiF6:Mn4+ phosphor by wet chemical etching of Si wafer

Abstract: A new method of synthesizing Mn-activated phosphor is presented The method uses only chemical etching of Si wafer in HF/H2O solution with the addition of an oxidizing agent KMnO4 The luminescence centers of red emission are ascribed to Mn4+ ions in the octahedral sites of potassium hexafluorosilicate (K2SiF6) The luminescence intensity becomes much stronger at higher temperatures, without largely changing its spectral feature

Method and apparatus for manufacturing semiconductor device, control program, and program recording medium

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which can simplify processes in comparison with the conventional methods, can reduce manufacturing cost, and can improve productivity; and to provide the manufacturing apparatus, the control program, and the program recording medium of the semiconductor device. SOLUTION: The method of manufacturing the semiconductor device includes: a film forming step of forming a SiO 2 film 104 on the pattern of a photoresist 103; an etching step of etching the SiO 2 film 104 so that the SiO 2 remains only in the sidewall section of the pattern of the photoresist 103; and a step of removing the pattern of the photoresist 103 and form the pattern of the SiO 2 film 104. COPYRIGHT: (C)2009,JPO&INPIT

High-Density Regular Arrays of Nanometer-Scale Rods Formed on Silicon Surfaces via Femtosecond Laser Irradiation in Water

Abstract: We report on the formation of high-density regular arrays of nanometer-scale rods using femtosecond laser irradiation of a silicon surface immersed in water. The resulting surface exhibits both micrometer-scale and nanometer-scale structures. The micrometer-scale structure consists of spikes of 5-10 µm width, which are entirely covered by nanometer-scale rods that are roughly 50 nm wide and normal to the surface of the micrometer-scale spikes. The formation of the nanometer-scale rods involves several processes: refraction of laser light in highly excited silicon, interference of scattered and refracted light, rapid cooling in water, roughness-enhanced optical absorptance, and capillary instabilities. As semiconductor processing reaches smaller and smaller feature sizes, much research is dedicated to the development of new methods for producing regular, nanometer-scale structures on solid surfaces. Lithography and chemical etching are powerful methods that offer control over the shape and size of structures, but they are often complex and costly. 1–3 In contrast, pulsed laser-assisted etching 4,5 is a simple but effective method for fabricating small structures directly onto a substrate. However, most of the cross sections of such structures are typically larger than the laser wavelength. 4–14

Controllable Preferential-Etching Synthesis and Photocatalytic Activity of Porous ZnO Nanotubes

Abstract: Porous ZnO nanotubes have been synthesized via a facile hydrothermal method based on a preferential etching strategy. The nanotubes have a nearly homogeneous size with about 250 nm diameter, 40 nm wall thickness, and 500 nm length. Nanoholes with diameters ranging from tens to hundreds of nanometers were created on the side wall of the tubular structure. Formation of the porous ZnO nanotubes resulted from preferential etching along the c axis and relatively slow etching along the radial directions due to the polar feature of the ZnO crystal. Superior photocatalytic activity of the porous ZnO nanotubes in the degradation of methyl orange compared to the other samples has been demonstrated, and the origin is mainly ascribed to the scattered nanoholes on the wall of the porous nanotubes. The influence factors and formation mechanism of the porous ZnO nanotubes were analyzed and discussed.

Silicon etch with passivation using plasma enhanced oxidation

Abstract: A method and apparatus for etching a silicon layer through a patterned mask formed thereon are provided. The silicon layer is placed in an etch chamber. An etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas is provided into the etch chamber. A plasma is generated from the etch gas and features are etched into the silicon layer using the plasma. The etch gas is then stopped. The plasma may contain OH radicals.

Nf3/h2 remote plasma process with high etch selectivity of psg/bpsg over thermal oxide and low density surface defects

Abstract: A method and apparatus for selectively etching doped semiconductor oxides faster than undoped oxides. The method comprises applying dissociative energy to a mixture of nitrogen trifluoride and hydrogen gas remotely, flowing the activated gas toward a processing chamber to allow time for charged species to be extinguished, and applying the activated gas to the substrate. Reducing the ratio of hydrogen to nitrogen trifluoride increases etch selectivity. A similar process may be used to smooth surface defects in a silicon surface.

On the wet etching of Pyrex glass

Abstract: This paper addresses a commonly raised question regarding wet etching of Pyrex glass: “How are the defects on the glass generated during etching process while most of the masking materials are chemically inert in the etching solution?” The response to this question relies in controlling the residual stress in the masking layer (its value, gradient and nature: compressive or tensile) and controlling the hydrophobicity of the mask surface. With this response, the solution for achieving a suitable process can be easily set up: a low stress masking layer (preferably performed by successive depositions) and a hydrophobic surface of the masking layer (easily achieved, for example by hard baking of the photoresist masking layer). Nevertheless, these factors must be correlated with a correct selection of the glass material (low content of oxides that gives insoluble products after the reaction with the etching solution) and a fast etch rate (achieved using highly concentrated hydrofluoric acid). The best reported results in the literature are analyzed for this perspective.

Tungsten-Based SOI Microhotplates for Smart Gas Sensors

Abstract: This paper is concerned with the design, fabrication, and characterization of novel high-temperature silicon on insulator (SOI) microhotplates employing tungsten resistive heaters. Tungsten has a high operating temperature and good mechanical strength and is used as an interconnect in high temperature SOI-CMOS processes. These devices have been fabricated using a commercial SOI-CMOS process followed by a deep reactive ion etching (DRIE) back-etch step, offering low cost and circuit integration. In this paper, we report on the design of microhotplates with different diameters (560 and 300 mum) together with 3-D electrothermal simulation in ANSYS, electrothermal characterization, and analytical analysis. Results show that these devices can operate at high temperatures (600degC ) well beyond the typical junction temperatures of high temperature SOI ICs (225degC), have ultralow dc power consumption (12 mW at 600degC), fast transient time (as low as 2-ms rise time to 600degC), good thermal stability, and, more importantly, a high reproducibility both within a wafer and from wafer to wafer. We also report initial tests on the long-term stability of the tungsten heaters. We believe that this type of SOI microhotplate could be exploited commercially in fully integrated microcalorimetric or resistive gas sensors.

An advanced reactive ion etching process for very high aspect-ratio sub-micron wide trenches in silicon

Abstract: This paper reports on a practical modification of the two-step time-multiplexed plasma etching recipe (also known as the Bosch process) to achieve high aspect-ratio sub-micron wide trenches in silicon. Mixed argon and oxygen plasma depassivation steps are introduced in between the passivation and etching phases to promote the anisotropic removal of the passivation layer at the base of the trench. Argon does not chemically react with polymers and silicon and removes the passivation layer only by physical sputtering. Therefore, it results in a highly anisotropic polymer etching process. This recipe can be easily integrated on conventional ICP equipment and the scalloping on the trench sidewall can potentially be reduced in size to less than 50 nm. To clean up all the passivation residues, a short oxygen plasma step is also added at the end of the cycle that effectively improves the uniformity of the etching profile over various opening sizes. Excellent anisotropy of the inserted argon depassivation step facilitates narrow trenches down to 130 nm wide and gap aspect-ratios as high as 40:1, extending the application of deep reactive ion etching (DRIE) processes into a new broad regime.

Manufacturing method of a silicon carbide semiconductor device

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.