Showing papers on "Memistor published in 2014"

MAGIC—Memristor-Aided Logic

Abstract: Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. While memristors are naturally used as memory, memristors can also be used for other applications, including logic circuits. In this brief, a memristor-only logic family, i.e., memristor-aided logic (MAGIC), is presented. In each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional memristor serves as an output. The topology of a MAGIC nor gate is similar to the structure of a common memristor-based crossbar memory array. A MAGIC nor gate can therefore be placed within memory, providing opportunities for novel non-von Neumann computer architectures. Other MAGIC gates also exist (e.g., and , or , not , and nand ) and are described in this brief.

Memristor Crossbar-Based Neuromorphic Computing System: A Case Study

Abstract: By mimicking the highly parallel biological systems, neuromorphic hardware provides the capability of information processing within a compact and energy-efficient platform. However, traditional Von Neumann architecture and the limited signal connections have severely constrained the scalability and performance of such hardware implementations. Recently, many research efforts have been investigated in utilizing the latest discovered memristors in neuromorphic systems due to the similarity of memristors to biological synapses. In this paper, we explore the potential of a memristor crossbar array that functions as an autoassociative memory and apply it to brain-state-in-a-box (BSB) neural networks. Especially, the recall and training functions of a multianswer character recognition process based on the BSB model are studied. The robustness of the BSB circuit is analyzed and evaluated based on extensive Monte Carlo simulations, considering input defects, process variations, and electrical fluctuations. The results show that the hardware-based training scheme proposed in the paper can alleviate and even cancel out the majority of the noise issue.

A Floating Analog Memristor Emulator Circuit

Abstract: This brief introduces a new floating memristor emulator circuit based on second-generation current conveyors and passive elements. A mathematical model to characterize the memristor behavior was derived, showing a good accuracy among HSPICE simulations and experimental results. An analysis of the frequency behavior of the memristor is also described, showing that the frequency-dependent pinched hysteresis loop in the current-versus-voltage plane holds up to 20.2 kHz. Theoretical derivations and related results are experimentally validated through implementations from commercially available devices, and the proposed memristor emulator circuit can easily be reproducible at a low cost. Furthermore, the emulator circuit can be used as a teaching aid and for future applications with memristors, such as sensors, cellular neural networks, chaotic systems, programmable analog circuits, and nonvolatile memory devices.

Polymer memristor for information storage and neuromorphic applications

Abstract: Polymermaterials have been considered as promising candidates for the implementation of memristor devices due to their low-cost, easy solution processability, mechanical flexibility and ductibility, tunable electronic performance through innovative molecular design cum synthesis strategy and compatibility with complementary metal oxide semiconductor (CMOS) technology as well. The digital-type polymer memristor behaves as resistive random access memory with non-volatility, high density, more speed, low power consumption, large ON/OFF ratio, high endurance and long retention, and is recognized as an appealing candidate for the next generation "universal memory". As a logic component, the analog-type memristor, with the ability to emulate the fundamental synaptic functions of short-term/long-term plasticity (STP/LTP), spike-timing dependent-plasticity (STDP), spike-rate dependent plasticity (SRDP) and "learningexperience" behaviors, can be used to construct artificial neural networks for neuromorphic computation. In this review, we shall attempt to summarize the recent progress in research on the materials, switching characteristics and mechanism aspects of two terminal polymer memristors, for both information storage and neuromorphic applications that inspire great interest in the industrial and academic communities.

Analog memristive memory with applications in audio signal processing

Abstract: Since the development of the HP memristor, much attention has been paid to studies of memristive devices and applications, particularly memristor-based nonvolatile semiconductor memory. Owing to its unique properties, theoretically, one could restart a memristor-based computer immediately without the need for reloading the data. Further, current memories are mainly binary and can store only ones and zeros, whereas memristors have multilevel states, which means a single memristor unit can replace many binary transistors and realize higher-density memory. It is believed that memristors can also implement analog storage besides binary and multilevel information memory. In this paper, an implementation scheme for analog memristive memory is considered. A charge-controlled memristor model is derived and the corresponding SPICE model is constructed. Special write and read operations are demonstrated through numerical analysis and circuit simulations. In addition, an audio analog record/play system using a memristor crossbar array is designed. This system can provide great storage capacity (long recording time) and high audio quality with a simple small circuit structure. A series of computer simulations and analyses verify the effectiveness of the proposed scheme.

Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems

Abstract: Neuromorphic computing system (NCS) is a promising architecture to combat the well-known memory bottleneck in Von Neumann architecture. The recent breakthrough on memristor devices made an important step toward realizing a low-power, small-footprint NCS on-a-chip. However, the currently low manufacturing reliability of nano-devices and the voltage IR-drop along metal wires and memristors arrays severely limits the scale of me-mristor crossbar based NCS and hinders the design scalability. In this work, we propose a novel system reduction scheme that significantly lowers the required dimension of the memristor crossbars in NCS while maintaining high computing accuracy. An IR-drop compensation technique is also proposed to overcome the adverse impacts of the wire resistance and the sneak-path problem in large memristor crossbar designs. Our simulation results show that the proposed techniques can improve computing accuracy by 27.0% and 38.7% less circuit area compared to the original NCS design.

A Native Stochastic Computing Architecture Enabled by Memristors

Abstract: A two-terminal memristor device is a promising digital memory for its high integration density, substantially lower energy consumption compared to CMOS, and scalability below 10 nm. However, a nanoscale memristor is an inherently stochastic device, and extra energy and latency are required to make a deterministic memory based on memristors. Instead of enforcing deterministic storage, we take advantage of the nondeterministic memory for native stochastic computing, where the randomness required by stochastic computing is intrinsic to the devices without resorting to expensive stochastic number generation. This native stochastic computing system can be implemented as a hybrid integration of memristor memory and simple CMOS stochastic computing circuits. We use an approach called group write to program memristor memory cells in arrays to generate random bit streams for stochastic computing. Three methods are proposed to program memristors using stochastic bit streams and compensate for the nonlinear memristor write function: voltage predistortion, parallel single-pulse write, and downscaled write and upscaled read. To evaluate these technical approaches, we show by simulation a memristor-based stochastic processor for gradient descent optimization, and k-means clustering. The native stochastic computing based on memristors demonstrates key advantages in energy and speed in compute-intensive, data-intensive, and probabilistic applications.

Memristor Multiport Readout: A Closed-Form Solution for Sneak Paths

Abstract: In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings The new method requires fewer reading steps compared to previously reported techniques, and has a very small impact on the memory density To verify the underlying theory, the proposed system is simulated using Synopsys HSPICE showing the ability to achieve a 100% sneak-path error-free memory In addition, the effect of quantization bits on the system performance is studied

A new memristor emulator and its application in digital modulation

Abstract: Since its inception many proposals and attempts have been reported on using the memristor in digital signal processing (DSP) circuits. Memristor-based DSP applications are mainly focusing on improving the performance of memories and in realizing synapses in neural networks. In most of the reported applications the verification of the proposed DSP circuits is made using mathematical-based memristor models. In this paper a new circuit for practical emulation of the memristor and its applications in memristor-based digital modulation is experimentally investigated.

Enabling back propagation training of memristor crossbar neuromorphic processors

Abstract: Recent studies have shown that memristor crossbar based neuromorphic hardware enables high performance implementations of neural networks at low power and in low chip area. This paper presents circuits to train a cascaded set of memristor crossbars representing a multi-layered neural network. The circuits presented implement back-propagation training and would enable on-chip training of memristor crossbars. On-chip training of memristor crossbars can be necessary to overcome the effect of device variability and alternate current paths within crossbars being used as neural networks. We model the memristor crossbars in SPICE in order capture alternate current paths and the impact of wire resistance. Our design can be scaled to multiple neural layers and multiple output neurons. We demonstrate the training of up to three layered neural networks evaluating non-linearly separable functions through detailed SPICE simulations. This is the first study in the literature we have seen that examines the implementation of back-propagation based training of memristor crossbar circuits. The impact of this work would be to enable the design of highly energy efficient and compact neuromorphic processing systems that can be trained to implement large deep networks (such as deep belief networks).

Neuromorphic Character Recognition System With Two PCMO Memristors as a Synapse

Abstract: Using memristor devices as synaptic connections has been suggested with different neural architectures in the literature. Most of the published works focus on simulating some plasticity mechanism for changing memristor conductance. This paper presents a neural architecture of a character recognition neural system using Al/Pr0.7Ca0.3MnO3 (PCMO) memristors. The PCMO memristor has an inhomogeneous barrier at the aluminum and PCMO interface which gives rise to an asymmetrical behavior when moving from high resistance to low resistance and vice versa. This paper details the design and simulations for solving this asymmetrical memristor behavior. Also, a general memory read/write framework is used to describe the running and plasticity of neural systems. The proposed neural system can be produced in hardware using a small 1 K crossbar memristor grid and CMOS neural nodes as presented in the simulation results.

Optimized implementation of memristor-based full adder by material implication logic

Abstract: Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.

BDD based synthesis of Boolean functions using memristors

Abstract: Very recently a new passive circuit element called memristor has been extensively investigated by researchers, which can be used for a variety of applications. This two-terminal device having few nanometer dimensions has been experimentally shown to possess both memory and resistor properties. This has also received great attention due to the fact that these devices can very easily be integrated on CMOS subsystems. Most of the logic design works in this context are based on material implication operation which can be very efficiently implemented using memristors. In this paper we propose an efficient realization of 2-to-1 multiplexer using memristors, and hence present a synthesis methodology that represents a given Boolean function as a Reduced Ordered Binary Decision Diagram (ROBDD) and then maps the same to memristor implementation.

ICE: inline calibration for memristor crossbar-based computing engine

Abstract: The emerging neuromorphic computation provides a revolutionary solution to the alternative computing architecture and effectively extends Moore's Law. The discovery of the memristor presents a promising hardware realization of neuromorphic systems with incredible power efficiency, allowing efficiently executing the analog matrix-vector multiplication on the memristor crossbar architecture. However, during computations, the memristor will slowly drift from its initial programmed state, leading to a gradual decline of the computation precision of memristor crossbar-based computing engine (MCE). In this paper, we propose an inline calibration mechanism to guarantee the computation quality of the MCE. The inline calibration mechanism collects the MCE's computation error through `interrupt-and-benchmark (I&B)' operations and predicts the best calibration time through polynomial fitting of the computation error data. We also develop an adaptive technique to adjust the time interval between two neighbor I&B operations and minimize the negative impact of the I&B operation on system performance. The experiment results demonstrate that the proposed inline calibration mechanism achieves a calibration efficiency of 91.18% on average and negligible performance overhead (i.e., 0.439%).

Reliability challenges in design of memristive memories

Abstract: The demand for highly scalable and low power memory has led to research in emerging technologies and devices. Among these devices, memristors has attracted increased attention as being a promising storage device. However, due to its nano-scale size it faces various types of reliability issues. In this study, we have reviewed the memristive mechanisms and reliability concerns existing in memristor memory design. Then, we have simulated the ionic drift memristor model in presence of the process variability. Next, by considering a normal distribution for the resistive distribution of memristors in LRS and HRS state we have shown the instabilities and probability of failure in read and write procedure of memristive memories, and highlighted the requisite and motivation for the reliability aware memristive circuit design.

Memristor based memories: Technology, design and test

Abstract: Today's memory technologies, such as DRAM, SRAM, and NAND Flash, are facing major challenges with regard to their continued scaling. For instance, ITRS projects that DRAM cannot scale easily below 40nm as the cost and energy/power are hard -if not impossible- to scale. Fortunately, the international memory technology community has been researching other alternative for more than fifteen years. Apparently, non-volatile resistive memories are promising to replace the today's memories for many reasons such as better scalability, low cost, higher capacity, lower energy, CMOS compatibility, better configurability, etc. This paper discusses and highlights three major aspects of resistive memories, especially memristor based memories: (a) technology and design constraints, (b) architectures, and (c) testing and design-for-test. It shows the opportunities and the challenges.

Memristor crossbar based multicore neuromorphic processors

Abstract: This paper describes memristor-based neuromorphic circuits for non-linear separable pattern recognition. We initially describe a memristor based neuron circuit and then show how multilayer neural networks can be constructed based on this neuron circuit. By applying neural network learning algorithms to these circuits, we demonstrate the learning of both linearly and non-linearly separable logic functions. The simulations are carried out in SPICE using a detailed memristor model so that the crossbar is simulated as accurately as possible. We also examine the system level performance of multicore memristor crossbar based neuromorphic processors. We consider the impact on on-chip routing, calculate the chip areas, and evaluate the timing of the systems in the study. The results indicate that such architectures can enable over 300,000 times energy efficiencies over traditional high performance computing architectures when processing large neural networks.

Memristor-based neuron circuit and method for applying learning algorithm in SPICE?

Abstract: The learning of nonlinearly separable functions in cascaded memristor crossbar circuits is described and the feasibility of using them to develop low-power neuromorphic processors is demonstrated. This is the first study evaluating the training of memristor crossbars through SPICE simulations. It is important to capture the alternate current paths and wire resistance inherent in these circuits. The simulations show that neural network learning algorithms are able to train in the presence of alternate current paths and wire resistances. The fact that the approach reduces the area by three times and power by two orders of magnitude compared with the existing approaches that use virtual ground opamps to eliminate alternate current paths is demonstrated.

Memristor crossbar-based unsupervised image learning

Abstract: This letter presents a new memristor crossbar array system and demonstrates its applications in image learning. The controlled pulse and image overlay technique are introduced for the programming of memristor crossbars and promising a better performance for noise reduction. The time-slot technique is helpful for improving the processing speed of image. Simulink and numerical simulations have been employed to demonstrate the useful applications of the proposed circuit structure in image learning.

Hybrid crossbar architecture for a memristor based memory

Abstract: This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 4 times the bit density of an STT-MRAM system and up to 11 times the bit density of an SRAM architecture. The proposed architecture is analyzed using a detailed SPICE analysis that accounts for the resistance of the wires in the memristor structure. Additionally, the memristor model used in this work has been matched to specific device characterization data to provide accurate results in terms of energy, area, and timing.

The stochastic modeling of TiO 2 memristor and its usage in neuromorphic system design

Abstract: Memristor, the fourth basic circuit element, has shown great potential in neuromorphic circuit design for its unique synapse-like feature. However, though the continuous resistance state of memristor has been expected, obtaining and maintaining an arbitrary intermediate state cannot be well controlled in nowadays memristive system. In addition, the stochastic switching behaviors have been widely observed. To facilitate the investigation on memristor-based hardware implementation, we built a stochastic behavior model of TiO2 memristive devices based on the real experimental results. By leveraging the stochastic behavior of memristors, a macro cell design composed of multiple parallel connecting memristors can be successfully used in implementing the weight storage unit and the stochastic neuron - the two fundamental components in neural network (NN)s, providing a feasible solution in memristor-based hardware implementation.

Hybrid memristor/RTD structure-based cellular neural networks with applications in image processing

Abstract: Cellular neural network (CNN) has been acted as a high-speed parallel analog signal processor gradually. However, recently, since the decrease in the size of transistor is going to approach the utmost, the transistor-based integrated circuit technology hits a bottleneck. As a result, the advantage of very large scale integration implementation of CNN becomes hard to really present, and further development of this era faces severe challenges unavoidably. In this study, two types of memristor-based cellular neural networks have been proposed. One type uses a memristor to replace the linear resistor in a conventional CNN cell circuit. And the other places a resonant tunneling diode (RTD) in this position and uses memristive synaptic connections to structure a hybrid memristor RTD CNN model. The excellent performances of the proposed CNNs are verified by conventional means of, for instance, stability analysis and efficient applications in image processing. Since both the memristor and the resonant tunneling diode are nanoscale, the size of the network circuits can be greatly reduced, and the integration density of the system will be significantly improved.

Memristor-based ternary content addressable memory (mTCAM) for data-intensive computing

Abstract: A memristor-based ternary content addressable memory (mTCAM) is presented. Each mTCAM cell, consisting of five transistors and two memristors to store and search for ternary data, is capable of remarkable nonvolatility and higher storage density than conventional CMOS-based TCAMs. Each memristor in the cell can be programmed individually such that high impedance is always present between searchlines to reduce static energy consumption. A unique two-step write scheme offers reliable and energy-efficient write operations. The search voltage is designed to ensure optimum sensing margins with the presence of variations in memristor devices. Simulations of the proposed mTCAM demonstrate functionalities in write and search modes, as well as a search delay of 2 ns and a search of 0.99 fJ/bit/search for a word width of 128 bits.

A memristor-based TCAM (ternary content addressable memory) cell

Abstract: This paper presents a Ternary Content Addressable Memory (TCAM) cell that employs memristors as storage element. The TCAM cell requires two memristors in series to perform the traditional memory operations (read and write) as well as the search and matching operations for TCAM; this memory cell is analyzed with respect to different features (such as memristance range and voltage threshold) of the memristors to process fast and efficiently the ternary data. A comprehensive simulation based assessment of this cell is pursued by HSPICE. Comparison with other memristor-based CAMs as well as CMOS-based TCAMs shows that the proposed cell offers significant advantages in terms of power dissipation, reduced transistor count and search/match operation performance.

Memristor based adders

Abstract: Currently memristors are being researched to offer logic and memory functions. Recently, ultra dense resistive memory arrays built from various two terminal semiconductor or insulator thin film devices have been demonstrated. This paper presents memristor-based designs of commonly used (ripple carry, conditional sum and parallel prefix) adders. The latency and area of these adders are compared.

A Study of the Memristor Models and Applications

Abstract: Before 1971, all the electronics were based on three basic circuit elements. Until a professor from UCBerkeley reasoned that another basic circuit element exists, which he called memristor; charact ...