Showing papers on "Mixed-signal integrated circuit published in 2003"

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

An all-digital analog-to-digital converter with 12-/spl mu/V/LSB using moving-average filtering

Abstract: A compact, high-resolution analog-to-digital converter (ADC) especially for sensors is presented. The basic structure is a completely digital circuit including a ring-delay-line with delay units (DUs), along with a frequency counter, latch, and encoder. The operating principles are: (1) the delay time of the DU is modulated by the analog-to-digital (A/D) conversion voltage and (2) the delay pulse passes through a number of DUs within a sampling (= integration) time and the number of DUs through which the delay pulse passes is output as conversion data. Compact size and high resolution were realized with an ADC having a circuit area of 0.45 mm/sup 2/ (0.8-/spl mu/m CMOS) and a resolution of 12 /spl mu/V (10 kS/s). Its nonlinearity is /spl plusmn/0.1% FS per 200-mV span (1.8-2.0 V), for 14-b resolution. Sample holds are unnecessary and a low-pass filter function removes high-frequency noise simultaneously with A/D conversion. Thus, the combination of this ADC and a digital filter that follows can eliminate an analog prefilter to prevent the aliasing before A/D conversion. Also, both this ADC can be shrunk and operated at low voltages, so it is an ideal means to lower the cost and power consumption. Drift errors can be easily compensated for by digital processing.

On-chip ramp generators for mixed-signal BIST and ADC self-test

Abstract: A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement results show excellent accuracy and programmability, up to only 0.6% of slope error and maximum integral nonlinearity error of /spl plusmn/175/spl mu/V. Experimental and theoretical results are in good agreement.

Efficient on-chip global interconnects

Abstract: We present circuits for a high-efficiency low-swing interconnect scheme suitable for the Smart Memories reconfigurable architecture. By using a separate supply, global clocking, and differential signaling, we reduce design complexity; and by using overdrive circuits, equalization techniques, and sense-amplifiers we retain high performance. A testchip built in a 1.8 V 0.18-/spl mu/m technology consumed <1pJ/bit for a 10 mm bus at 1 GHz, a power savings over full-swing signaling of up to 10 x, and demonstrated amplifier input offset voltages of under 100 mV.

Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit

Abstract: A general purpose interface tile of a first integrated circuit includes a plurality of micropads. A second integrated circuit may be stacked on the first integrated circuit such that signals from the second integrated circuit are communicated through the micropads and the interface tile to other circuitry on the first integrated circuit. Similarly, signals from the first integrated circuit are communicated through the interface tile and the micropads to the second integrated circuit. In the event that the first integrated circuit is a programmable logic device having a programmable interconnect structure, the interface tile is part of and hooks into the programmable interconnect structure and provides a general purpose mechanism for coupling signals from the second integrated circuit to the programmable interconnect structure and/or for coupling signals from the programmable interconnect structure to the second integrated circuit.

Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts

Abstract: There are many applications for true, unpredictable random numbers. For example the strength of numerous cryptographic operations is often dependent on a source of truly random numbers. Sources of random information are available in nature but are often hard to access in integrated circuits. In some specialized applications, analog noise sources are used in digital circuits at great cost in silicon area and power consumption. These analog circuits are often influenced by periodic signal sources that are in close proximity to the random number generator. We present a random number generator comprised entirely of digital circuits, which utilizes electronic noise. Unlike earlier work [11], only standard digital gates without regard to precise layout were used.

A low-cost test solution for wireless phone RFICs

Abstract: This article describes an IBM approach for testing high-volume, complex RFICs at a fraction of the cost of the integrated circuit. This approach uses a personal computer, a fast benchtop dc parametric analyzer, and RF-to-analog circuits to test an RFIC during the manufacturing process. The described system and methodology are specifically designed for high-volume test, where test cost is extremely important; they are not recommended for lower-volume products (less than 1 million per month). This article describes the system architecture and discusses design, maintenance, and implementation considerations. The system is designed to reduce the cost of a complex RFIC manufacturing test to equal that of a discrete component, such as a resistor or capacitor. Given the relatively easy implementation and the drastic cost reduction associated with the test solution, this architecture establishes a new standard for the future of RF test. In fact, this architecture may result in the fastest RF tester currently available.

A new family of very low-voltage analog circuits based on quasi-floating-gate transistors

Abstract: A new family of very low-voltage analog circuits is introduced. These circuits do not show the GB degradation that characterizes other low-voltage approaches based on floating-gate transistors. The proposed approach is validated with experimental results of a CMOS mixer in 0.5-/spl mu/m CMOS technology with 0.7-V input signal swing that operates on a single 0.8-V supply with transistor threshold voltages of 0.67 V.

A 114-dB 68-mW Chopper-stabilized stereo multibit audio ADC in 5.62 mm/sup 2/

Abstract: A multibit delta-sigma audio stereo analog-to-digital converter has been developed. It employs a fifth-order single-loop 17-level delta-sigma modulator with an input feedforward gain stage. A second-order mismatch shaping (DEM) circuit is utilized to remove tones and nonlinearities caused by capacitor mismatch of the feedback digital-to-analog converter. The implementation of the DEM block introduces minimum latency into the delta-sigma feedback loop. Chopper stabilization is applied to the first integrator to eliminate the 1/f noise. The converter achieves 114-dB dynamic range and -105-dB total harmonic distortion over the 20-kHz audio band. This single chip includes stereo analog modulators, bandgap reference, serial interface, and a two-stage decimation filter, occupies 5.62-mm/sup 2/ active area in a 0.35-/spl mu/m double-poly, three-metal CMOS process and dissipates only 55-mW power in the analog circuits.

Power converter having improved control

Abstract: A power converter using a microcontroller is disclosed herein. In one embodiment, the power converter can be a digital flyback or forward converter. The microcontroller may have a digital pulse-width-modulation (PWM) controller, arithmetic logic unit (ALU) core, internal random access memory (RAM), read-only memory (ROM), and one or more analog-to-digital (A/D) and digital-to-analog (D/A) converters. For a fast dynamic response in an inner current control loop, an analog comparator is used to provide analog-based current control. The analog comparator may compare a signal representative of the current flowing in the power converter against a voltage reference, which can be programmable. The analog comparator may be integrated with the digital microcontroller into single integrated circuit (IC) chip. Furthermore, the power converter can send signals for the status of various conditions (e.g., output voltage levels, current levels, errors, etc.) or can receive signals for system control commands (e.g., output voltage, current protection levels, standby-mode for a lowest power consumption, normal mode, and power ON or OFF commands) via a serial communication port.

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

Abstract: In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.

Three-dimensional integration: technology, use, and issues for mixed-signal applications

Abstract: Three-dimensional (3-D) integration provides opportunities in large-scale integration of mixed-signal and general system-on-chip applications with improved performance, through increased density and mixing of different active and passive technologies. This paper reports a novel low-thermal-budget 3-D fabrication technique-multilayers with buried structures (MLBS) and an analysis of its applicability to mixed-signal integration. The MLBS technique uses a low temperature of 450/spl deg/C to transfer a single-crystal silicon layer over a processed wafer consisting of buried in-plane and out-of-plane interconnects obtained through a dual Damascene process. Devices can continue to be processed on this transferred layer. Electrical characteristics of MOS capacitors (D/sub it/=4.7/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/) and 3-D integrated planar CMOS transistors (3-D CMOS), fabricated using MLBS, are consistent with integration requirements. Our analog analysis includes an investigation of thermal effects important to analog applications with continuous operation of transistors in forward active bias, as well as of the coupling isolation derived from use of a ground-plane. Use of high density local interconnectivity improves the thermal properties of 3-D CMOS over that of silicon-on-insulator, and use of a ground plane is shown to lead to an improvement of better than 8 dB in coupling isolation.

System and method for integrating a digital core with a switch mode power supply

Abstract: A digital core embodied within a semiconductor die that requires plural separate power supply voltage domains is situated within any of a variety of integrated circuit packaging technologies. Within the integrated circuit package including this semiconductor die also exists a switch mode DC-to-DC voltage converter, preferably a synchronous step-down regulator powering the entire integrated circuit from one supply voltage. The components contained within the integrated circuit package along with the semiconductor die include the switch mode power supply's power switching transistors, inductor core and windings, digital open-loop output voltage fixing circuitry, output capacitors and substrate for mounting said components when integrated within a packaging technology that does not already include a substrate.

A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications

Abstract: A self-controllable voltage level (SVL) circuit which can supply a maximum dc voltage to an active-load circuit on request or can decrease the dc voltage supplied to a load circuit in standby mode was developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such circuits fitted with SVL circuits can retain data even in the standby mode. The standby power of an 8-bit 0.13-/spl mu/m CMOS ripple carry adder (RCA) with an on-chip SVL circuit is 8.2 nW, namely, 4.0% of that of an equivalent conventional adder, while the output signal delay is 786 ps, namely, only 2.3% longer than that of the equivalent conventional adder. Moreover, the standby power of a 512-bit memory cell array incorporating an SVL circuit for a 0.13-/spl mu/m 512-bit SRAM is 69.1 nW, which is 3.9% of that of an equivalent conventional memory-cell array. The read-access time of this 0.13-/spl mu/m SRAM is 285 ps, that is, only 2 ps slower than that of the equivalent SRAM.

Analog and mixed signal modelling with SystemC-AMS

Abstract: SystemC is likely to become more and more important for the design of digital circuits from the specification down to the RT-level. Complex systems often contain analog components. This paper introduces concepts for the extension of the SystemC methodology for the specification and design of analog and mixed signal systems. The concepts are illustrated on a telecommunication system including digital hardware and software, analog filter and an analog environment.

Internally varying analog circuits minimize power dissipation

Abstract: We review several techniques that make possible the dynamic variation of analog circuits internally, without affecting their input-output characteristics. Particular attention is paid to companding (dynamic gain scaling), dynamic impedance scaling, dynamic biasing, and dynamic structure variation. A mixture of more than one of these techniques is appropriate in some cases. We use filters as a specific example of dynamical analog circuits and place particular emphasis on avoiding or eliminating transients at the output of such circuits, which would normally occur due to such dynamic variations. By allowing for dynamic internal variations, the power dissipation of such circuits can be lowered and can be made to depend on how demanding the task at hand is. This allows for large savings of energy drain over time, thus making possible long battery life in portable equipment.

Contactless integrated circuit reader

Abstract: The present invention relates to a contactless integrated circuit reader operating by inductive coupling, comprising an antenna circuit for sending an alternating magnetic field, circuits for applying an alternating excitation signal to the antenna circuit and circuits for modulating the amplitude of an antenna signal present in the antenna circuit according to data to be sent. The reader includes circuits for simulating the operation of a contactless integrated circuit, arranged to inhibit the application of the excitation signal to the antenna circuit and to apply a load modulation signal to the antenna circuit when data is to be sent. The load modulation signal is capable of disturbing a magnetic field sent by another contactless integrated circuit reader and of being detected by the other contactless integrated circuit reader.

A physical compact model of DG MOSFET for mixed-signal circuit applications- part I: model description

Abstract: To use double-gate (DG) MOSFET for mixed-signal circuit applications, especially for circuits in which the two gates are independently driven, such as in the case of dynamic-threshold and fixed-potential-plane operations, physical compact models that are valid for all modes of operations are necessary for accurate design and analysis. Employing physically rigorous current-voltage (I-V) relationship in subthreshold and above-threshold regions as asymptotic cases, we have constructed a model that joins the two operating regions by using carrier-screening functions. We have included consistently source/drain series resistance, low drain-field mobility, and small-geometry effects of drain-induced barrier lowering (DIBL), MOS interface mobility, velocity saturation and channel-length modulation (CLM) with validation from two-dimensional (2-D) distributed simulation. All model parameters can be extracted from large-signal I-V characteristics in dc conditions with given geometrical data. Parameter extraction methods and verification from simulation are presented in Part II.

Three dimensional CMOS devices and integrated circuits

Abstract: Three dimensional devices and, integrated circuits are attractive options for overcoming barriers in device and interconnect scaling, offering an opportunity to continue the CMOS performance trend. This paper reviews the process technology and associated design issues in three dimensional devices and integrated circuits.

A new successive approximation architecture for low-power low-cost CMOS A/D converter

Abstract: A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm/sup 2/ with the TSMC 0.35-/spl mu/m single poly quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs.

An architecture for a configurable mixed-signal device

Abstract: The mixed-signal programmable system-on-chip (PSOC) architecture for high-volume low-cost applications is presented. Programmable analog, digital, and clocking circuits are combined with flash memory and a microcontroller to provide a platform for single-chip solutions for low-cost consumer applications. Both programmable analog and digital circuits are designed to support a moderate level of abstraction, balancing flexibility against cost and performance. A rough comparison of alternative approaches based on functionality and cost is presented.

A 5V complementary-SiGe BiCMOS technology for high-speed precision analog circuits

Abstract: A novel complementary-SiGe BiCMOS technology developed for ultra-high speed precision analog circuits is presented. The modular process offers comparable NPN and PNP performance utilizing unique interface and SiGe base process.

Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies

Abstract: This paper presents a methodology for high-level synthesis of continuous-time linear analog systems. Synthesis results are architectures of op-amps, sized resistors and capacitors such that their ac behavior and total silicon area are optimized. Bounds for op-amp dc gain, unity-gain frequency, input, and output impedances are found as a byproduct of synthesis. Subsequently, a circuit synthesis tool can be used to synthesize the op-amps of an architecture. The paper details the architecture generation technique. Architecture generation produces alternative architectures for a system specification using the tabu search heuristic. Its main advantages over traditional methods is that it is application independent, does not require a library of block connection patterns, and is simple to implement. The paper also discusses the hierarchical, two-step parameter optimization that guides architecture generation. Experiments showed that linear analog systems operating at low/medium frequencies (like telecommunication systems and filters) can be synthesized in a reasonably long time and with reduced effort.

Analog Logic: Continuous-Time Analog Circuits for Statistical Signal Processing

Abstract: This thesis proposes an alternate paradigm for designing computers using continuoustime analog circuits. Digital computation sacrifices continuous degrees of freedom. A principled approach to recovering them is to view analog circuits as propagating probabilities in a message passing algorithm. Within this framework, analog continuous-time circuits can perform robust, programmable, high-speed, low-power, cost-effective, statistical signal processing. This methodology will have broad application to systems which can benefit from low-power, high-speed signal processing and offers the possibility of adaptable/programmable high-speed circuitry at frequencies where digital circuitry would be cost and power prohibitive. Many problems must be solved before the new design methodology can be shown to be useful in practice: Continuous-time signal processing is not well understood. Analog computational circuits known as “soft-gates” have been previously proposed, but a complementary set of analog memory circuits is still lacking. Analog circuits are usually tunable, rarely reconfigurable, but never programmable. The thesis develops an understanding of the convergence and synchronization of statistical signal processing algorithms in continuous time, and explores the use of linear and nonlinear circuits for analog memory. An exemplary embodiment called the Noise Lock Loop (NLL) using these design primitives is demonstrated to perform direct-sequence spread-spectrum acquisition and tracking functionality and promises order-of-magnitude wins over digital implementations. A building block for the construction of programmable analog gate arrays, the “soft-multiplexer” is also proposed. Thesis Supervisor: Neil Gershenfeld Title: Associate Professor

Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS

Abstract: High-level synthesis is highly demanded for managing the complexity of analog and mixed-signal system designs. However, synthesis methods are currently in their infancy. The absence of a high-level specification notation is an important limitation for the development of efficient synthesis methods. This paper presents a behavioral model and a VHDL-AMS subset for high-level synthesis of analog and mixed-signal systems. The model (named aBlox) offers a composition semantics for functionality description and an orthogonal declarative mechanism for expressing the performance requirements of a system. The model was developed after analyzing a large number of systems for telecommunication, signal processing, control engineering, and analog computing. The model expresses the meaning of: 1) analog and digital data; 2) continuous and event-driven functionality (behavior); 3) analog performance attributes; and 4) analog-digital interactions. The aBlox model serves as a foundation for defining a semantically sound VHDL-AMS subset for synthesis. Also, the VHDL-AMS subset is identified so that its constructs can be mapped to architectures of circuits. We introduce several restrictions to the VHDL-AMS instructions, such that their semantics match that of the aBlox model. To motivate the usefulness of the model and the VHDL-AMS subset, we present a case study that uses VHDL-AMS inputs.

Initial sizing of analog integrated circuits by centering within topology-given implicit specifications

Abstract: We present a novel technique to automatically calculate an initial sizing of analog circuits that conforms to good design practice. The method is purely (DC) simulation-based and does not need symbolic design equations or user design knowledge. It identifies the space of feasible design parameters based on implicit specifications, which arise from the circuit topology. A sizing centered within this space is obtained by iteratively solving a maximum volume ellipsoid problem on approximations to the feasible parameter space. The result is well-suited as initial sizing because it safely satisfies all implicit specifications. Experimental results demonstrate the efficiency and reliability of our method.

Integrated circuit with power monitoring/control and device incorporating same

Abstract: A power management integrated circuit for monitoring a parameter of a power system includes: an analog front end operative to receive and at least one of amplify, attenuate and filter analog signals representative of at least one of voltage and current in a power system to produce modified analog signals; an analog to digital converter operative to produce digital signals; the logic coupled with the analog to digital converter operative to receive the digital signals and produce a power parameter and the logic includes a processor core; a random access memory coupled with the logic operative to store the power parameter and the logic is operative to implement a setpoint to detect when the power parameter is outside a determined range; and a digital output coupled with the first logic and the digital output is useable to control a switching circuit outside the power management integrated circuit.

Current-driven wire planning for electromigration avoidance in analog circuits

Abstract: Electromigration due to insufficient wire width can cause the premature failure of a circuit. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years, especially with analog circuits. It is therefore an important reliability issue to consider current densities already in the physical design stage. We present a new methodology capable of routing analog multi-terminal signal nets with current-dependent wire widths. It is based on current-driven wire planning which effectively determines all branch currents prior to detailed routing. We also discuss successful applications of our methodology in commercial analog circuit design.

Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance

Abstract: In this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for mixed-signal applications. Our results show that, in LAC MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/I/sub D/ etc.) down to the 70-nm technology node, in addition to an improvement in drive current and other parameters over a wide range of channel lengths. A systematic comparison on the performance of amplifiers and CMOS inverters with CON and LAC MOSFETs is also performed. The tradeoff between power dissipation and device performance is explored with detailed circuit simulations for both CON and LAC MOSFETs.