Showing papers on "Parasitic capacitance published in 1988"

Zero-voltage-switching multi-resonant technique-a novel approach to improve performance of high frequency quasi-resonant converters

Abstract: The power transistor in zero-current-switched quasiresonant converters (ZCS-QRCs) suffers from excessive voltage stress, and the converter regulation characteristics and stability are adversely affected by parasitic oscillations caused by the junction capacitance of the rectifying diode. A novel, multiresonant switch concept is proposed to overcome these problems. A unique multiresonant network arrangement results in absorption of all parasitic components, including transistor output capacitance, diode junction capacitance, and transformer leakage inductance, in the resonant circuit. This results in favorable switching conditions for all devices. Experimental results show that ZVS multiresonant converters are superior to ZVS-QRCs due to reduced transistor voltage stress and improved load range and stability. >

Broad band monolithic microwave active inductor and application to a miniaturized wide band amplifier

Abstract: A broadband monolithic microwave active inductor composed of two FETs and a resistor is proposed. The most significant innovation of the active inductor is considered to be a novel circuit structure which suppresses stray capacitance to yield a much higher-frequency operating range than a spiral inductor. The inductor is small and independent of the inductance value. The FET-oriented configuration allows a denser chip circuitry packing. A 0.1-10-GHz miniaturized wideband amplifier realized using the active inductors is described. >

Line-to-ground capacitance calculation for VLSI: a comparison

Abstract: A comparison is made between various approximations of the line-to-ground capacitance problem in a VLSI environment. It is shown that with up-to-date dimensions, the simple parallel-plate model is no longer adequate. However, easy-to-use and fast-to-compute formulas exist that result in accurate and reliable capacitance values. >

Scanning method and apparatus for current signals having large dynamic range

Abstract: There is disclosed herein apparatus and a method for scanning information off a processing plane where the information is contained in a current signal having a very small amplitude and which can change signs and vary in amplitude by as much as five orders of magnitude. The preferred embodiment of the apparatus uses a pair of CMOS pass transistors connected to the individual processing elements and the row select lines. The pass transistors, when turned on, couple the output current from the processor containing the desired information to a column line. The column line is connected to a current to voltage converter in the form of a differential input amplifier having a non linear feedback circuit comprised of two diode connected CMOS transistors operating in the subthreshold region. The non linear feedback circuit provides an exponential transfer function which compresses the dynamic range of the output current from the processor to a smaller and more useable output range for an output voltage. The negative feedback to the inverting input coupled to the column line stabilizes the voltage on the column line to virtual ground thereby eliminating the delay associated with driving the parasitic capacitance of the column line with the very small output current from the processor in an attempt to substantially change the voltage of the column line.

Capacitance free generation and detection of subpicosecond electrical pulses on coplanar transmission lines

Abstract: By reanalyzing an earlier experiment to generate subpicosecond pulses using photoconductive switches (M.B. Ketchen, et al., Appl. Phys. Lett., vol.48, pp.751-753, 1986), it is shown that to first order, the sliding-contact generation site has no capacitance. This conclusion is further supported by a double sliding-contact experiment where, to first order, neither the generation nor the detection site has any capacitance. This result removes the parasitic capacitance of the electrical circuit as one of the major difficulties to short electrical pulse generation using photoconductive switches. >

GHz on-silicon-wafer probing calibration methods

Abstract: Three calibration/correction techniques for on-silicon-wafer S-parameter measurements to 18 GHz were assessed by comparing calibration standards on sapphire and silicon. The effect of these techniques was evaluated by measuring large and small devices, connected to large and small pads. Equivalent circuit models for the calibration standards on silicon are presented. In addition, a new technique for on-wafer S-parameter measurements of backside collector devices is presented. >

A digital readout technique for capacitive sensor applications

Abstract: The difference between two capacitors is measured digitally using a charge redistribution technique incorporating a comparator, MOS switches, a successive approximation register, and a digital-to-analog converter. The technique is insensitive to comparator offset and parasitic capacitance, and the effect of MOS switch charge injection is measured and canceled. Extensive measurements have been made from test chips fabricated in 3- mu m CMOS technology. Detection of percent differences of >

GaAs monolithic implementation of active circulators

Abstract: A GaAs monolithic three-transistor signal circulator for 0.2- to 2-GHz applications was developed and tested. The circuit consists of three FETs with gates of 150- mu m width and 0.5- mu m length, three capacitors, and seven GaAs resistors. The resulting chip size is 1.1 mm*1.0 mm on a substrate of thickness 0.15 mm. The ability afforded by monolithic construction techniques to locate the active devices in close proximity to each other and avoid interconnecting circuitry stray capacitance is critical to the high-frequency operation of the device. The three-terminal device demonstrated a 6-dB insertion loss and an 18-dB directivity over the above frequency range. >

Design, optimization, and construction of a DC SQUID with complete flux transformer circuits

Abstract: The design of a complete dc SQUID with a flux transformer input circuit is discussed. The flux coupling circuits introduce a substantial capacitance across the SQUID and give rise to many resonances which may couple strongly to the SQUID dynamics. Both effects lead to multiple modes in the SQUID dynamics and consequently to excess noise. For a low-noise SQUID with smooth characteristics, our analysis and practical considerations suggest signal coupling via an intermediary transformer. This method allows simultaneous optimization of the SQUID parameters, minimizing the parasitic capacitance, control over the resonances, and good inductance matching to practical magnetometer coils. A model is developed to optimize the structure: it describes the whole circuit with the help of a suitably modified autonomous SQUID, provided that the system is free from multiple modes due to resonances or large parasitic capacitance. Following these design principles, we have built a dc SQUID, primarily for use in biomagnetic research, but also well suited for other applications. The fabrication of the SQUID and the high-quality electronics especially suitable for multiple-SQUID devices is presented. The SQUIDs showed smooth characteristics, and the lowest measured noise of our complete SQUID is % MathType!MTEF!2!1!+-% feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLn% hiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr% 4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq-Jc9% vqaqpepm0xbba9pwe9Q8fs0-yqaqpepae9pg0FirpepeKkFr0xfr-x% fr-xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaaGymaiaac6% cacaaIZaGaey41aqRaaGymaiaaicdadaahaaWcbeqaaiabgkHiTiaa% iAdaaaGccqqHMoGrdaWgaaWcbaGaaGimaiaac+caaeqaaOWaaOaaae% aacaWGibGaamOEaaWcbeaaaaa!428B!$1.3 \times 10^{ - 6} \Phi _{0/} \sqrt {Hz} $, indicating the success of the design.

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Abstract: Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized. >

Resonant PWM inverter linked DC-DC convertor using parasitic impedances of high-voltage transformer and its applications to X-ray generator

Abstract: A description is given of a resonant DC-DC converter that uses both the leakage inductances and stray winding capacitances of a high-voltage transformer as LC resonant components and the input capacitance of high-voltage cables as a smoothing DC capacitor. The converter incorporates a pulsewidth-modulated (PWM) control based on a high-frequency inverter at constant frequency to adjust output over a wide range of loads, Its application to an X-ray generator power supply system is reported. A computer-aided state-variable analysis of the circuit is presented. Experimental results using a prototype transformer are given, covering output voltage control characteristics, maximum output power, and converter output waveforms in the X-ray generator. >

Semi-insulating blocked planar BH GaInAsP/InP laser with high power and high modulation bandwidth

Abstract: A high-power, high-speed GaInAsP/InP laser operating at a 1.3μm wavelength is described. The laser is obtained with three epitaxial growth steps and has semi-insulating InP blocking layers resulting in low parasitic capacitance. A 3 dB bandwidth of 14.7 GHz together with 38 mW output power has been achieved.

LC filter device having magnetic resin encapsulating material

Abstract: An LC filter device includes a dielectric substrate having opposing sets of coil electrode patterns and capacitor electrode patterns. Each set of coil electrode patterns forms an inductive element, and each set of capacitor electrode patterns forms a capacitive element. The inductive and capacitive elements are interconnected to form an LC circuit configuration. The dielectric substrate is encapsulated by a resin coating. The resin coating includes a magnetic material, such as a high frequency ferrite powder, to increase the inductance of the LC filter and to reduce the stray capacitance of the LC filter.

An analytical approach to the capacitance-voltage characteristics of double-heterojunction HEMTs

Abstract: The two-dimensional electron gas concentration and capacitance in AlGaAs/GaAs/AlGaAs double-heterojunction high-electron-mobility transistors (DH-HEMTs) are calculated as a function of gate voltage using simple iterative solutions of analytical equations. The results show very good agreement with experimental data, as well as with characteristics predicted by complex numerical methods. The calculations are extended to predict the capacitance-voltage characteristics in the presence of parasitic conduction when the gate does not fully control the two-dimensional gas. The developed charge control and capacitance models are easy and inexpensive to run. They are therefore very useful for microwave circuit designs. Furthermore, they can be used for performance prediction and design optimization of DH-HEMTs. The influence of technological parameters, such as layer thickness and aluminum composition, on device performance are presented. >

Method and system for eliminating cross-talk in thin film transistor matrix addressed liquid crystal displays

Abstract: In a liquid crystal display, and more particularly, in a thin film transistor matrix addressed liquid crystal display, a method and means are provided for assuring the presence of a constant RMS voltage waveform on the data lines. This eliminates uncertainty in the voltage levels on a pixel element caused by parasitic capacitance effects between the data lines and the pixel electrodes. The present invention is also particularly applicable to both binary level and gray scale level devices. Means for carrying out the present method are illustrated in both analog and digital form.

Issues regarding the capacitance of 1-10 MHz transformers

Abstract: Capacitive modeling issues are addressed, particularly with respect to minimizing leakage inductance. Reasonable assumptions about the winding configuration and the distribution of voltage around it are made. The total electrical energy stored in the winding when a voltage is applied is then calculated and partitioned into the differential and common-mode parts. A description of how the common-mode current flows is discussed, and the tradeoff between leakage inductance and capacitance is quantified. Some experimental results are provided. >

SPICE models for power MOSFETs: an update

Abstract: Five existing power MOSFET models intended for use with SPICE simulations are reviewed and compared. Methods used for simulating the gate-drain capacitance are evaluated. The internal JFET employed in two of the models is found to be usually unnecessary. A simple two-value capacitance model is recommended. The performance of this model is demonstrated with data obtained from 200 kHz forward converter. >

Reducing EMI in switch mode power supplies

Abstract: In general, as the operating frequency of a switch-mode converter increases, the task of EMI (electromagnetic interference) suppression becomes more difficult. Many times, a reduction in power supply size is negated by bulky input and output filters. Additional mechanical and printed circuit board design iterations have resulted due to EMI difficulties. With these difficulties in mind, the author examines the types of EMI, their origins, and methods of measurements. He considers the minimization of the required 'after the fact' filtering. If this is done early in the design phase, some of the extra design iterations can hopefully be eliminated. To accomplish this, various components and circuit configurations are examined. A 100 W forward converter was used to verify most of the methods discussed. Specifically, it was shown that, by controlling parasitic capacitance, significant reductions can be made in the conducted EMI. A byproduct of controlling these parasitics is the fact that the conducting-loop area is reduced and therefore the radiated EMI is also reduced. >

20 GHz bandwidth low-noise HEMT preamplifier for optical receivers

Abstract: A broadband, low-noise HEMT preamplifier is designed for very high-speed fibre-optic transmission systems. A 20 GHz 3dB down bandwidth and 7.6pA/√(Hz) averaged input equivalent noise current density from 100 MHz to 18 GHz are achieved using inductor peaking techniques and low stray capacitance chip resistors.

SPIDER: capacitance modelling for VLSI interconnections

Abstract: An efficient method is presented to model the parasitic capacitance of VLSI interconnections. It is valid for conductors in a stratified medium which is considered to be a good approximation for the Si-SiO/sub 2/ system of which ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a 'spider' of edges. The model has very low complexity as compared to previously presented models and achieves a high degree of precision within the range of validity of the stratified medium. >

Semiconductor memory circuit with improved bit line precharge circuit

Abstract: A dynamic memory circuit provided with an improved bit line reference voltage control circuit realized by a small capacitance of an adjustment capacitor is disclosed. The memory circuit includes a short-circuiting circuit for setting each pair of bit lines at an intermediate voltage of a power source voltage, a capacitor for lowering the intermediate voktage according to charge division based on a ration of a capacitance of the adjustment capacitor and a total capacitance of the bit lines, and a boot-strap circuit for operatively causing a level reduction more than the power source voltage in the capacitor.

MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform

Abstract: A resistor is connected to an input portion of a CMOS inverter. An input of the CMOS inverter is affected by a time constant of an RC circuit comprising the resistor and gate stray capacitance of the CMOS inverter. In addition, there is provided an n channel MOS transistor having a drain and a source connected to both ends of the resistor, respectively, and a gate connected to an input signal source. Only in the rising portion of an input signal, the n channel MOS transistor is turned on, so that the resistor is bypassed. Thus, a waveform of output of the CMOS inverter is not delayed at the falling portion. Only at the rising portion, the waveform thereof is delayed due to the time constant of the above described RC circuit.

A new capacitance transducer for industrial applications

Abstract: An absolute capacitance measuring device based on the fundamental charge, capacitance and voltage relationship is described. It consists of a pair of CMOS analogue switches and a current integration amplifier, resulting in a simple capacitance transducer capable of providing a programmable measurement frequency ranging from 100 kHz to 5 MHz. This makes the transducer suitable for component concentration measurement of multicomponent flow processes involving conductive fluids. The initial circuit design is followed by a mathematical model of the transducer. Parametric analysis of this model is used to optimise both the sensitivity and stability of the transducer. A discrimination of 0.01 pF in 10 pF full scale is achieved. In measurements of capacitance with one plate grounded, the problem of stray capacitance arises. A novel switched guard method has been devised which reduces the effect of strays by a factor of 0.0025 at an operating frequency of 1 MHz.

Tunable short monopole top-loaded antenna

Abstract: A short monopole RF antenna tuned over a predetermined RF frequency band in response to binary control signals includes a conductive tubular radiating element extending generally at right angles to a ground plane on which the antenna is mounted. A conductive top load inductively coupled to the element extends approximately parallel to the ground plane so that stray capacitance subsists between the ground plane and top load. The antenna is tuned in response to the control signals to a frequency in the band by selectively short-circuiting different plural series-connected inductors in proximity with the top load. Plural leads extend through the interior of the tubular element between a source of the control signals and switches for selectively short circuiting the inductors. The inductors are electrical conductors in a tube-like structure. The leads extend through the interior of the tube-like structure. Electrical conductors in the tube-like structure are in a return path to the control signal source. The switch for each inductor includes a pair of diodes positioned outside of the tube-like structure. The lead for each inductor extends through the tube-like structure and is electrically insulated from the electrical conductors. A feed for the antenna is connected to the tube at a location in proximity to the ground plane. An inductor is connected between the location where the feed is connected to the tube and the ground plane for approximately matching the feed to the tuned element for low frequencies in the RF range.

An 8ns 256k Bicmos Ram

Abstract: A 256Kh ECL RAM achieving less than 400mW power consumption at 50MHz operation, and 150mW at standby will be descrihed in this paper. The RAM was fabricated using 1 . O p m performance Bipolar CMOS (Hi-BiCMOS) technology. 64Kb ECL RAMS with access times of 5 to 7ns and 256Kb CMOS SRAM of 21ns were reported previously’ ress access time and low-power consumption, an ECL-MOS level shifter and a powerdown circuit technique were developed. Figure 1 shows the 1.0p.m Hi-BiCMOS device structure. In the bipolar part of the device, parasitic capacitances are reduced by scaling. The polysilicon emitter structure has been employed to achieve a cutoff frequency of 9GHz. In the CMOS segment of the chip, the gate lengths were scaled to 0.9@ (N-channel) and 1.lp.m (P-channel) with 20nm gate oxide. The use of 1.0pm design rules permits layout of a memory cell with high-resistance polysilicon load in 57.4W2 and a chip in 4.09mm x 8.60mm. Basic characteristics of this device are shown in Table 1. A block diagram of the RAM is shown in Figure 2. An ECL input signal level is received by an input buffer and is shifted to a MOS signal level by an ECL-MOS level shifter. X and Y decoders select one memory cell in the memory cell array, divided into 8 blocks, to reduce propagation delay time (tpd) of a wordline and active power consumption of the memory cell array. This results in 400mW active power.

Overvoltage-protective device

Abstract: Voltage-dividing resistors, being connected in parallel to a switching element to be protected, create control voltage which is responsive to voltage applied to the switching element, to supply the same to a gate of a field effect transistor. The field effect transistor is connected in parallel to the switching element, to conduct when the control voltage exceeds a threshold value for passing overvoltage absorbing current, while causing high-frequency shorting across the switching element by its parasitic capacitance.

ECL to CMOS transition amplifier

Abstract: When processing logic signals in ECL and CMOS circuitry it is necessary to adjust the logic levels when going from one type of circuitry to another. A problem which occurs is that smearing of a logic level occurs due to poor rise and fall times in a level adjusting amplifier. The rise and fall times can be improved by the level adjusting amplifier load circuit comprising the series connection of the source-drain paths of first and second N-channel transistors (20, 22), the parasitic capacitance of the drain of the first transistor (20) at a node (23), and by connecting the gate of the second transistor (22) to the node. In operation, when the first transistor (20) is non-conductive and the node (23) is charged, the second transistor (22) is operating in the triode or linear region of its characteristic in spite of its gate being at the voltage of the node. When the first transistor (20) is rendered conductive then both transistors (20, 22) are fully conductive and the starting discharge current is high. An amplifier including a symmetrical load is disclosed in FIG. 4.

Semiconductor laser module incorporating driver circuit therein

Abstract: In a semiconductor laser module incorporating a driving circuit therein, which contains a semiconductor laser mounted on an electronic cooling element and a semiconductor laser driving IC within the same package, is provided an electrode lead on a stem for mounting a semiconductor laser, for connecting the semiconductor laser with a board carrying a driving IC and the dimensions of the electrode lead are defined so as to reduce the stray capacitance and the parasitic inductance and to optimize the thermal resistance. A gap of a value not to introduce an increase of an unnecessary inductance between the semiconductor laser mounting portion and the driver IC mounting board is provided to spatially divide the semiconductor laser mounting portion and the driver IC mounting board. Thereby, the inflow of the heat generated in a driver IC into a semiconductor laser mounted on an electronic cooling element can be suppressed without degrading the high speed modulation characteristics in the giga-bits band.

Surface-acoustic-wave device with a capacitance coupled between input and output

Abstract: A surface-acoustic-wave device includes a surface-acoustic-wave filter with a capacitance connected in parallel between its input and output leads. The capacitance improves the attenuation characteristic of the device on the high-frequency side of the center frequency.