Showing papers on "Parasitic element published in 2014"

Understanding the Effect of PCB Layout on Circuit Performance in a High-Frequency Gallium-Nitride-Based Point of Load Converter

Abstract: The introduction of enhancement-mode gallium-nitride-based power devices such as the eGaN FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the printed circuit board (PCB) layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET-based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This paper will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design, providing a 40% decrease in parasitic inductance over the best conventional PCB design.

Package Parasitic Inductance Extraction and Simulation Model Development for the High-Voltage Cascode GaN HEMT

Abstract: This paper presents the development of a simulation model for high-voltage gallium nitride (GaN) high-electron-mobility transistors (HEMT) in a cascode structure. A method is proposed to accurately extract the device package parasitic inductance, which is of vital importance to better predict the high-frequency switching performance of the device. The simulation model is verified by a double-pulse tester, and the results match well both in terms of device switching waveform and switching energy. Based on the simulation model, an investigation of the package influence on the cascode GaN HEMT is presented, and several critical parasitic inductances are identified and verified. Finally, a detailed loss breakdown is made for a buck converter, including a comparison between hard switching and soft switching. The results indicate that the switching loss is a dominant part of the total loss under hard-switching conditions in megahertz high-frequency range and below 8~10 A operation current; therefore, soft switching is preferred to achieve high-frequency and high-efficiency operation of the high-voltage GaN HEMT.

Impact of Parasitic Elements on the Spurious Triggering Pulse in Synchronous Buck Converter

Abstract: This paper derives a circuit-level analytical model for describing the mechanism of the spurious triggering pulse in the gate-source voltage of the synchronous MOSFET (SyncFET) in the synchronous buck converter. The model takes into account not only the parasitic capacitances and inductances of the control MOSFET (CtrlFET) and the SyncFET, but also the reverse recovery characteristics of the body diode of the SyncFET. An exhaustive investigation into the impact of all these factors on the spurious triggering pulse is conducted. The spurious triggering pulse can be attributed to two factors. The first one is the positive gate voltage caused by the displacement current through the gate-drain capacitance of the SyncFET, due to the increase in the drain-source voltage. The second one is the negative source voltage caused by the voltage drop across the source inductance of the SyncFET, due to the decrease in the drain current. It is discovered that the gate impedance of the SyncFET would exert different influence on the magnitude of the spurious triggering pulse, depending on the contributions of these two factors. Experimental results affirm that variation in the magnitude of the spurious triggering pulse with each parasitic element can be correctly inferred by the proposed model. Design guidelines for enhancing spurious turn-on immunity are advanced.

Novel Modified De-Sauty Autobalancing Bridge-Based Analog Interfaces for Wide-Range Capacitive Sensor Applications

Abstract: In this paper, we propose novel fully analog uncalibrated readout circuits for wide-range capacitance estimation. The working principle is based on a modified De-Sauty ac bridge configuration where two capacitances and two resistances are employed. Through the use of a voltage controlled resistor and of a suitable feedback loop, an accurate estimation over a wide range of the sensor capacitance variation is possible, also without the knowledge of the other bridge component values. The first two proposed solutions are able to estimate, experimentally, ~1.5 decades (optimized range: [25-840 nF]) and more than 3 decades [900 pF-1.1 μF] of capacitive variations, respectively, ensuring, continuously, the bridge equilibrium condition; the third interface allows the evaluation of the sensor capacitance also outside this condition, increasing the capacitive variation decades to more than 4 [81 pF-1.1 μF]. The proposed topologies have been also modified to detect the capacitive sensor parasitic resistance. In this case, experimental results on PCB have demonstrated the capability to simultaneously estimate ~ 1.7 capacitive [2-100 nF] and 1.5 resistive variation decades [33 kΩ-1.2 MΩ]. Finally, a suitable optimization of the operating range of the first proposed solution, obtained through a proper passive components sizing, has been performed with the aim to employ the commercial humidity sensor HCH-1000 in a high accuracy (11.4 bits) RH% detection.

Design considerations for GaN HEMT multichip halfbridge module for high-frequency power converters

Abstract: This paper discusses the design of a multichip Gallium-Nitride (GaN) power module for high frequency power conversion. The module is designed with HRL 600 V Gallium-Nitride (GaN) enhancement mode HEMT device. To exploit the capability of fast switching with low loss from high voltage GaN devices, different layout structures have been analyzed to reduce power loop parasitic inductance and improve switching performance. The approach investigated in this paper is based on a multi-chip module where small current rated dies are placed in parallel to achieve higher current handling capability. Moreover, a transmission-line type gate structure has been proposed to minimize the gate loop inductance and reduce the gate voltage ringing. Finite-Element-Analysis (FEA) and switching circuit simulation show that the multi-layer power loop design can effectively reduce the gate loop inductance and voltage overshoot on the devices. This multi-layer design also improves current sharing of the multi-chip module during switching operation. The transmission-line gate design is also proved in both simulation and experiment to be effective for reducing the gate loop inductance as well as gate loop ringing.

Study of the effects of parasitic inductances and device capacitances on 1200 V, 35 A SiC MOSFET based voltage source inverter design

Abstract: SiC MOSFET can switch five to ten times faster compared to state of the art Si IGBT. Due to that SiC MOSFET based power converter can be lighter in weight, highly efficient, compact in size compared to Si IGBT based power converters. But the parasitic inductance in the power circuit will not allow SiC MOSFET to switch to its full potential due to very high device voltage overshoot, sustained oscillation in line currents and device voltages, high EMI noise injected in the control circuit etc. Therefore it is very important to know the behavior of the switching characteristics of the device at different parasitic condition. In this paper switching behavior of a 1200V, 35 A, SiC MOSFET is tested extensively in different parasitic condition. A limiting value of these inductances is provided to build a voltage source inverter with SiC MOSFET utilizing its full switching potential.

Drain-Induced Barrier Lowering and Parasitic Resistance Induced Instabilities in Short-Channel InSnZnO TFTs

Abstract: Effect of short-channel induced instabilities in InSnZnO-based thin-film transistors (TFTs) caused by combination of the drain induced barrier lowering (DIBL) and parasitic resistance is reported. As the active channel length decreased below a critical value of around 8 μm, the draincurrent (2.81 μA) are abruptly increased and N-shaped behavior of the transconductance are observed due to the formation of additional current path in the channel. The magnitude of subgap density of states is also depended on the channel size. The higher value of parasitic resistance RSD (~42 kg) and DIBL coefficient (76.8 mV/V) in short-channel ITZO TFT devices are also discussed.

Investigation of parasitic elements for coupling reduction in multiantenna hand‐set devices

Abstract: This article investigates parasitic radiating structures for coupling reduction between two 900MHz planar inverted-F antennas (PIFAs) in a hand-held device. Measurement of the initial prototype shows that a maximum isolation enhancement of more than 8 dB is achieved with a single parasitic element. This is followed by optimization of the parasitic structure for compactness, improved bandwidth, and tuning capability. First, different techniques for miniaturization are employed to obtain 60% less footprint with a 22 mm x 15 mm meandered parasitic element. Second, it is demonstrated that the isolation bandwidth can be increased by employing several parasitic radiators with different lengths. Finally, it is presented that the operation of a handheld device, as well as the coupling reduction technique, is compromised in proximity to the human body. For the first time, a miniaturized electronically tunable parasitic radiating element is designed to compensate for the detuning of the coupling reduction technique and adjusting its resonance to achieve maximum isolation between two handset PIFAs. Measurements of the fabricated prototype show 810–960 MHz tuning range. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:1–10, 2014.

Simultaneous online estimation of junction temperature and current of IGBTs using emitter-auxiliary emitter parasitic inductance

Abstract: A novel method is presented for online estimation of the junction temperature (Tj) of semiconductor chips in IGBT modules, based on the voltage drop (VEE') across the parasitic inductor that exists between the main emitter (E) and auxiliary emitter (E) terminals. The peak amplitude of the voltage drop (VEE') was found to depend on the junction temperature at a known current and DC link voltage. Also, the collector current can be estimated simultaneously, by integrating VEE' without the use of any additional sensors. Measurement circuits were implemented to estimate Tj and the current, and their results are discussed. The results of these measurement circuits when implemented in a real power electronic (PE) converter to estimate Tj and current in real time are also presented. This method opens up a full set of new opportunities for engineers and designers to better understand the behavior and performance of high power modules in real PE applications.

Impact of ringing on switching losses of wide band-gap devices in a phase-leg configuration

Abstract: This paper investigates the effects of ringing on the switching losses of wide band-gap (WBG) devices in a phase-leg configuration. An analytical switching loss model considering the parasitic inductance, stray resistance, devices' junction capacitances, and reverse recovery characteristics of the freewheeling diode is derived to identify the switching energy dissipation induced by damping ringing. This part of energy is found to be at most the reverse recovery energy and the energy stored in the parasitics, which is a small portion of the total switching energy. But the parasitic ringing causes interference between two devices in a phase-leg (i.e., cross talk). It is observed that during the turn-on transient of one device, the resonance among parasitics results in high overshoot voltage on the complementary device in a phase-leg. It worsens the cross talk, leading to large shoot-through current and excessive switching losses. The analysis results have been verified by double pulse test with a 1200 V SiC MOSFETs based phase-leg power module.

Contact Effects in Amorphous InGaZnO Thin Film Transistors

Abstract: Control of the source-drain contact properties in amorphous InGaZnO semiconductor active layer is relevant since a high series resistance in the source-drain contacts causes degradation of electrical performance, particularly affecting short channel devices. We developed a method to extract the current-voltage characteristics of the injection contact, assuming that contact effects are negligible in long channel devices and by introducing a modified gradual channel approximation (quasi-two-dimensional model), to take into account for short channel effects. The present method allows to extract the parasitic resistance by using devices with only two different channel lengths. Assuming a transmission line scheme for the contact resistance and SCLC transport for the current density flowing along the vertical direction though the IGZO bulk, we have been able to evaluate the variation with ${\rm V}_{{\rm ds}}$ of contact resistance at source and drain electrodes.

Variable capacitance element and high-frequency device

Abstract: A high-frequency device includes an antenna coil, a variable capacitance element, and an RFIC. The variable capacitance element is configured by capacitor units in each of which a ferroelectric film is sandwiched between capacitor electrodes, and a capacitance value changes according to a control voltage applied between the capacitor electrodes. A control voltage application circuit configured by a plurality of resistance elements of different resistance values, and a resistance element of the variable capacitance element unit configured to apply a control voltage to the variable capacitance element are arranged in a layered manner above the capacitor unit. Thus, a variable capacitance element and a high-frequency device that includes a control voltage application circuit eliminating problems such as distortion due to active elements and growing IC size along with complication of circuit architecture, and ensuring reliability on impact due to falling or the like, are provided.

Miniaturized CPW‐FED UWB antenna with dual frequency rejection bands using stepped impedance stub and arc‐shaped parasitic element

Abstract: In this article, we propose the design of a coplanar waveguide (CPW)-fed circular slot antenna, with dual frequency rejection characteristics for ultra-wideband communication applications. The dual frequency rejection function is realized by inserting a stepped impedance stub (SIS) inside the circular ring radiation patch and by using an arc-shaped parasitic element (ASPE) along the circular ring radiation patch. The center frequencies of these rejection bands can be controlled by adjusting the dimensions of the SIS and the ASPE. The antenna has been designed, optimized, and fabricated, and its performance has been verified through measurements, which show that it can operate across a wide bandwidth ranging from 2.7 to 11.6 GHz with a VSWR < 2, and that it provides dual-band rejection characteristics at both the WLAN band and the X-band. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:783–787, 2014

A 30-MHz isolated push-pull VHF resonant converter

Abstract: A new isolated push-pull very high frequency (VHF) resonant DC-DC converter is proposed. The primary side of the converter is a push-pull topology derived from the Class EF2 inverter. The secondary side is a class E based low dv/dt full-wave rectifier. A two-channel multi-stage resonant gate driver is applied to provide two complementary drive signals. The advantages of the converter are as follows: 1) the power isolation is achieved; 2) the MOSFETs and diodes are under soft-switching condition for high efficiency; 3) the voltage stress of the MOSFET is much reduced; 4) the parasitic inductance and capacitance can be absorbed. A 30~36 VDC input, 50-W/ 24-VDC output, 30-MHz prototype has been built to verify the functionality.

Damping impact on dynamic analysis of LLC resonant converter

Abstract: In this paper, the small-signal model of LLC resonant converter is derived using extended describing function (EDF) methodology and the dynamics of the LLC resonant converter are studied based on the small signal model taking into account the circuit parasitic resistance. When designing the controller, this damping effect induced by the parasitic resistance is usually neglected. While it will be shown in this paper that for large transformer turns ratio, the secondary side parasitic resistance introduces significant damping in the resonant tank. A controller is designed for an example LLC circuit. It is shown that the control loop phase margin and the cross over frequency are highly dependent on the damping factor, which should be considered in the control loop design to have the desired transient performance. The experimental verification is provided as well.

Multi-beam smart antenna for wlan and pico cellular applications

Abstract: Multi-beam smart antenna for WLAN and cellular applications preferably has a steerable antenna system with a dipole antenna element located at the center of a ground plane. A first conductor is oriented parallel and collinear with a second conductor, and the ground plane is located therebetween. Each of first parasitic elements is positioned substantially parallel to the dipole element, and arranged on the upper-side of the ground plane in an array. Each of second parasitic elements is positioned parallel to the dipole element, and arranged on the underside of the ground plane in the same predetermined array. A plurality of switching elements connect parasitic elements and the ground plane to form reflective elements. Each parasitic element and corresponding parasitic element are oriented parallel and collinear with each other. A switching controller controls the switching elements to alter the antenna system's beam pattern by selectively activating or deactivating the reflective elements.

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

Abstract: Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (fT). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

Effect of Parasitic Elements on the Performance of Buck-Boost Converter for PV Systems

Abstract: In the proposed study, MOSFET device used in buck-boost converter for PV systems is studied. The parameter of MOSFET Rds(on) is varied and its effect on output voltage is studied. The parasitic elements in inductor and capacitor such as resistance on buck-boost converter performance are studied. From the proposed study it has been found that the effect of parasitic resistance in capacitor is less as compared to parasitic resistance effect of inductor. Also the proposed study gives better insight into parasitic effect of Printed Circuit Board and losses incurred due to the same. In PV systems buck-boost converter is used to convert solar energy to electrical energy which is then stored in battery to drive the loads. These parasitic elements will have considerable effect on the performance of buck-boost converter such as efficiency and output voltage as validated by experimental results. DOI: http://dx.doi.org/10.11591/ijece.v4i6.6855

Parasitic Inductance Cancellation for Surface Mount Shunt Capacitor Filters

Abstract: Parasitic mutual inductance between the input and output loops of a shunt capacitor filter limits the attenuation obtainable at high frequencies. This paper presents compact designs for integrated cancellation coils for surface mount shunt capacitor filters that enable these filters to be effective from megahertz to gigahertz frequencies. Computer inductance extraction tools are used to optimize the filter performance. Experiments are performed to validate the designs. A lumped element model of the filter describes the secondary parasitics that affect the performance and ultimately determine the bandwidth of the filter.

Antenna apparatus with an integrated proximity sensor and methods

Abstract: Wireless wide area network (WWAN) antenna with integrated sensor and methods of using the same. In one embodiment, an antenna subsystem and proximity sensing subsystem share a grounded antenna component/parasitic element. The parasitic element can be used to broaden the operating band of the antenna feeding component and provide an input (via a capacitance change) to a proximity sensor. The parasitic element is, in one embodiment, coupled in parallel to the proximity sensor allowing for a reduction in noise due to increased isolation between the antenna subsystem and the sensing subsystem.

A pattern-reconfigurable parasitic patch antenna using BAR and HPND PIN Diode

Abstract: A pattern reconfigurable parasitic patch antenna using BAR and HPND PIN Diode is proposed. With parasitic element and mutual coupling technique, the presented antenna achieved beam switching at five phi of 0°, 45°, 135°, 225° and 315°. This is realized by four parasitic element surrounded a driven element. Each of the parasitic is shorted to the ground via a shorting pin. The ON and OFF state condition is control by the PIN Diode switch that embed to each parasitic element. This research studies the performance of different PIN Diode of BAR-5002v and HPND-4005 in realizing the beam switching application.

SiC-JFET in half-bridge configuration - parasitic turn-on at current commutation

Abstract: This paper describes the effect of parasitic turn-on in SiC-semiconductors. The device under test is a half-bridge with 1700V normally-on SiC-JFETs. The half bridge contains 32 chips in parallel, 64 chips in total, resulting in a current rating of 480A. The module design follows the strip-line concept as published in [1]. Parasitic inductance in the power circuit amplifies the effect of parasitic turn-on. Gate inductance outside the module as well the inductance of gate and source sub-circuits inside the module play an important role in minimizing the parasitic turn-on [2, 3, 4]. To fully utilize SiC-devices in fast switching applications, an overall low inductance design is absolutely required. Thus, in combination with a special gate-drive concept, the effect of the parasitic turn-on will be reduced. The SiC-JFET shows superior performance in terms of switching losses even with some parasitic turn-on.

Modified Charge Amplifier for Stray Immune Capacitance Measurements

Abstract: It is shown theoretically and by experimentation that the ac stray immune capacitance meter based on the charge amplifier circuit can be modified to reduce the effects of the parasitic capacitance across the feedback capacitor. This is achieved by simply introducing a unity gain buffer amplifier within the circuit loop.

Evolution of 200V lateral-IGBT technology

Abstract: In this paper, an ideal lateral insulated gate bipolar transistor (LIGBT) using 0.25μm Silicon-on-insulator (SOI) BiC-DMOS process has been presented. We achieved the significant improvement of the 200V n-type LIGBT (n-LIGBT) current capability by applying hole and electron injection control, optimizing the N+/P+ widths in emitter region, shrinking the emitter-collector pitch, thinning the thickness of the gate insulator, reducing parasitic resistance and optimizing the profile of P-base impurity. The proposed device achieved the current increase by more than double compared with the previous technology. In addition, we improved short circuit capability of n-LIGBT by optimizing the structure and impurity profile. With the proposed n-LIGBT and other optimized devices, we have been able to realize 57% shrinkage in the PDP scan driver IC size compared with the previous one.

Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes

Abstract: We investigate in this work an original contact architecture to address 64 nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment. Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations. It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography. When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances. At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10 nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width W and supply voltage VDD taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption.

Investigation of false triggering mechanism

Abstract: This paper discusses a problem that a half-bridge circuit can generate, namely a false trigger by high-speed switching transition. In general, a false trigger occurs by charging a gate–source capacitance because of high-speed voltage transition and influx of current via a reverse transfer capacitance. Therefore, it is thought that the ratio of the input capacitance and the reverse transfer capacitance is important to check whether a false trigger occurs. However, we find another reason and propose a novel assumption. A novel false triggering mechanism appears by considering the source-side parasitic inductance. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Multi-path parallel optical component for high-speed transmission and assembling method thereof

Abstract: The invention discloses a multi-path parallel optical component for high-speed transmission and the assembling method thereof. The optical component comprises a parallel optical fiber coupling and aligning component, a lining plate, a chip carrier, a photoelectric chip array set and a driving circuit chip set, wherein the photoelectric chip array set is attached to the lining plate, the driving circuit chip set is attached to the lining plate, a through hole is formed in the middle of the chip carrier, the chip carrier is attached to the lining plate, the photoelectric chip array set and the driving circuit chip set are made to be arranged in the through hole in a penetrating mode, and the thickness difference between the driving circuit chip set and the chip carrier is preset; the driving circuit chip set is connected with the photoelectric chip array set and a circuit wire on the periphery of the through hole in the chip carrier in a routing mode, and the photoelectric chip array set is coupled and aligned with the parallel optical fiber coupling and aligning component. According to the multi-path parallel optical component, the routing length between the driving circuit chip set and the photoelectric chip array set and the routing length between the driving circuit chip set and the circuit wire on the chip carrier can be reduced, parasitic inductance and capacitance generated by routing are reduced greatly, and the high-speed signal transmission capacity is improved.

An ultra-low-power fully integrated ultrasound imaging CMUT transceiver featuring a high-voltage unipolar pulser and a low-noise charge amplifier

Abstract: In this paper, we report on the development of a fully-integrated, low-power analog frontend circuit, consisting in a high-voltage unipolar pulser and a low-noise charge amplifier, specifically designed for 1D CMUT arrays operating in the 1–15 MHz range. The proposed circuit comprises a high-voltage unipolar pulser, a T/R switch, and a low-noise charge amplifier (LNA), which were carefully co-designed in order to minimize the overall parasitic capacitance and power consumption. The high-voltage pulser allows generating up to 100-V unipolar pulses. The T/R switch was designed to achieve sufficient isolation of the LNA during transmission together with a low parasitic resistance in on state. The LNA is based on a capacitive feedback topology providing sufficient bandwidth and better noise-power performance than commonly adopted trans-resistance topologies. Chip prototypes were fabricated using a BCD-SOI technology available at STMicroelectronics. Experimental characterization results are achieved in conjunction with a 10 MHz CMUT linear array developed for medical imaging applications.

A New Approach for Low Voltage CMOS based on Current-controlled Conveyors

Abstract: In his paper a new current-controlled conveyor (CCCII) in CMOS technology is presented. It features, low supply voltage (±0.7), low power consumption, low circuit complexity, rail to rail operation and wide range parasitic resistance ( ). The circuit has been successfully employed in a multifunction biquad filter. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.