Showing papers on "Spice published in 1996"

Mixed analog-digital VLSI devices and technology

Abstract: Contents: Introduction: Mixed Analog-Digital Chips The MOSFET: Introduction and Qualitative View MOSFET DC Modeling MOSFET Small-Signal Modeling Technology and Available Circuit Components Layout Appendices: Additional MOS Transistor Modeling Information A Set of Benchmark Tests for Evaluating MOSFET Models for Analog Design A Sample Spice Input File.

Mosfet Modeling with Spice: Principles and Practice

Abstract: 1. SPICE Modeling and the Dominance of CMOS Technology. 2. SPICE Modeling and the Formalism of Model Building. 3. The Semiconductor Physics of MOS Structures. 4. A Comparison of Analytical and Numerical Results. 5. The Level 1 Model. 6. The Level 2 Model. 7. The Level 3 Model. 8. BSIM. 9. HSPICE Level 28. 10. BSIM2. 11. BSIM3. 12. MOS Model 9. 13. The Active Device Capacitance. 14. Accounting for Systematic Process Variations. 15. Circuit Level Correlation of Models and Hardware. 16. New Model Candidates. 17. The Future of Device Models for Circuit Simulation. APPENDICES. A. An Executive Summary of the Various Models. B. Channel Length and Width. C. The Final Model Equations. D. The Extracted HSPICE Level 28 Model. E. The Binned BSIM2 Model. INDEX.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

Abstract: A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

Modeling substrate effects in the design of high-speed Si-bipolar ICs

Abstract: In the design of high-speed IC's, the influence of the substrate on circuit performance must be considered carefully. Therefore, in this paper the contribution of the p/sup -/ substrate and channel stopper to the equivalent circuits of Si-bipolar transistors and bond pads are theoretically and experimentally investigated up to very high frequencies. Improved equivalent substrate circuits, well suited for standard circuit simulators (e,g., SPICE), are derived and checked by numerical simulation using a new simulator (called SUSI). The validity of both the numerical simulation results and the equivalent circuits are verified by on-wafer measurements up to 20 GHz. Finally, the simulator was successfully applied to investigate noise coupling via the substrate.

A distributed SPICE-model of a solar cell

Abstract: In this paper, a distributed SPICE-model for a solar cell is worked out. Special attention is paid to the problems of nonhomogeneous current distribution and the effective series resistance. Elaborate experimental techniques have been used to determine the model parameters. They are based on the I-V characteristics, the small signal impedance, and the open-circuit voltage decay measurements. The SPICE simulation results are compared with the measured static and dynamic characteristics of a solar cell. We found satisfactory agreement concerning the static characteristics, whereas there is discrepancy in the dynamic characteristics. This is because the SPICE-model of a p-n junction diode contains only one time constant. It is found that two time constants are necessary for accurate description of the dynamic performance. The techniques and methodologies developed here are applicable to other junction diodes operating at high frequencies or under transient conditions.

HEAT: hierarchical energy analysis tool

Abstract: This paper presents an algorithm for the estimation of power in static CMOS digital circuits using a stochastic approach. The salient feature of this approach is that it can be used to estimate the power of reasonably large digital circuits in a very short time, due to its hierarchical nature. Here, the given circuit is first partitioned into smaller sub-circuits. Then, the sub-circuits are modeled using state transition diagrams (stds), and the steady-state probabilities associated with the various states are computed by treating them as irreducible Markov chains. Finally, the energy associated with each sub-circuit is computed, and the total energy of the circuit is obtained by summing up the energies of its constituent sub-circuits. In the proposed hierarchical approach, the energies associated with various edges in a subcircuit are calculated only once using SPICE and these values are used several times; this results in large savings in computation time. Another advantage of the proposed approach is that we can accommodate switching activities at the transistor level and not necessarily at gate or higher levels. Experimental results show that the estimated power is in close agreement with the actual power obtained from exhaustive SPICE simulations, but the computation time required by the proposed approach is orders of magnitude less than that of SPICE.

Current controlled oscillator based on translinear conveyors

Abstract: A current controlled oscillator based on translinear current conveyors is presented. The oscillation frequency can be varied proportionally to the bias current. The oscillator uses two CCCII+s, and two grounded capacitors. SPICE simulation results agree with the theory.

Analysis of crosstalk and field coupling to lossy MTLs in a SPICE environment

Abstract: This paper proposes a circuit model for lossy multiconductor transmission lines (MTLs) suitable for implementation in modern SPICE simulators, as well as in any simulator supporting differential operators. The model includes the effects of a uniform or nonuniform disturbing field illuminating the line and is especially devised for the transient simulation of electrically long wideband interconnects with frequency dependent per-unit-length parameters. The MTL is characterized by its transient matched scattering responses, which are computed including both dc and skin losses by means of a specific algorithm for the inversion of the Laplace transform. The line characteristics are then represented in terms of differential operators and ideal delays to improve the numerical efficiency and to simplify the coding of the model in existing simulators. The model can be successfully applied to many kinds of interconnects ranging from micrometric high-resistivity metallizations to low-loss PCBs and cables, and can be considered a practical extension of the widely appreciated lossless MTL SPICE model, which maintains the simplicity and efficiency.

Accurate simultaneous switching noise estimation including velocity-saturation effects

Abstract: Simultaneous switching noise (SSN) on power supply lines is caused by the large switching transient currents flowing through parasitic inductances at the chip-package-pin interface. A new expression to estimate SSN in CMOS circuits that includes the velocity saturation effects seen in the short-channel MOSFETs is derived. SPICE Level 3 simulation results show that the formula predicts the SSN more accurately as compared to existing approaches for submicron processes even at reduced supply voltages.

High performance CMOS current comparator design

Abstract: The paper describes some design aspects in the implementation of CMOS current comparators. More specifically, techniques for offset and charge-injection compensations are discussed in detail, and some basic topologies for compensated current comparators are presented and compared by SPICE simulations. Moreover, a novel compensated fully differential current comparator is proposed which achieves a very high performance. It provides a sensitivity as low as 20 nA and a switching time better than 30 ns with a 0.5 /spl mu/A input step current while dissipating 45 /spl mu/W.

A sensitive Pirani vacuum sensor and the electrothermal SPICE modelling

Abstract: A sensitive micro-Pirani vacuum sensor has been fabricated. With effective schemes of ambient-temperature compensation and stabilization, it is capable of measuring vacuum pressure linearly from 1 torr down to 10 −7 torr, a three orders-of-magnitude improvement in resolution over conventional gauges. A special electrothermal SPICE model, complementary to the conventional analog representation of thermal parameters, is also proposed. It allows a high-level sensor-circuit integrated simulation based on the most fundamental principle and thermal variables. Good agreement between the measured data obtained from a constant-temperature readout circuit and the simulation result is demonstrated.

E-T based statistical modeling and compact statistical circuit simulation methodologies

Abstract: A new statistical parameter extraction methodology which translates actual process variations into SPICE model parameter variations is presented. This methodology uses E-T data to extract SPICE model parameters and guarantees that its extraction results match measured variations. We have applied this methodology to an industrial 0.5 /spl mu/m process. Excellent, overall I-V curve fit for multiple device geometries is achieved. A compact statistical circuit design technology that improves upon the typical/worst/best case methodology is also presented.

CMOS class-AB current mirrors for precision current-mode analog-signal-processing elements

Abstract: CMOS class-AB current mirrors for high-precision current-mode analog-signal-processing elements are described. The class-AB configuration allows us to reduce the offset error caused by device mismatch, the nonlinearity distortion, and power consumption. The offset error due to the device mismatch is greatly reduced by the reduction of the bias current. The class-AB current-mirror has less sensitivity to the mismatch since the bias current relative to the signal current can be reduced. The excellent precision is confirmed by Monte Carlo simulation and SPICE based on 1 /spl mu/m CMOS LSI parameters.

Improved solar array power point model with SPICE realization

Abstract: An improved and simplified formulation is given for a solar array current-voltage model. This model curve matches a specified maximum power point (i,v) specification, in addition to the open-circuit and short-circuit specifications. The improved model has a simplified numerical solution, which is practical for SPICE simulation of orbital-scale electrical power systems. This paper presents the mathematical development of the solar array model solution, and the form of the necessary Newton/Raphson equations. The iterative nonlinear solution is then realized in a SPICE model of the solar array, which is then demonstrated in an orbital-time-scale satellite power system simulation.

An efficient CMOS bridging fault simulator: with SPICE accuracy

Abstract: This paper presents an alternative modeling and simulation method for CMOS bridging faults. The significance of the method is the introduction of a set of generic-bridge tables which characterize the bridged outputs for each bridge and a set of generic-cell tables which characterize how each cell propagates a logically undefined input. These two sets of tables are derived dynamically for a specific design by using a SPICE circuit simulator. Then they can be used by any logic fault simulator to simulate bridging faults. In this way, the proposed method can perform very fast bridging fault simulation yet with SPICE accuracy. The paper shows how these two sets of tables are derived and used in a parallel pattern fault simulator. Experimental results on ISCAS85 benchmarks are promising.

Parameterized layout synthesis, extraction, and SPICE simulation for MEMS

Abstract: A suite of software tools which implements parameterized layout synthesis and SPICE simulation for surface-micromachined micro-electrical-mechanical systems (MEMS) is presented. These tools and techniques are demonstrated by using the design of a MEMS linear resonator as an example, and the various stages of this design are examined, including the generation of the circuit layout from performance specifications, the simulation of the devices, and the testing of actual fabricated resonators.

Early effect modeling in SPICE

Abstract: The approximations made in the Early effect formulation of the SPICE Gummel-Poon bipolar junction transistor (BJT) model were reasonable when the model was first developed but introduce unnecessary inaccuracies when modeling the output conductance of modern BJTs. In this paper, we give the reason the original approximations were made, present a new way to plot data to best show the Early effect, and detail a new, consistent, coupled method to determine forward and reverse Early voltages.

Interrater agreement in SPICE-based assessments: some preliminary results

Abstract: The international SPICE Project intends to deliver an ISO standard on software process assessment. This project is unique in software engineering standards in that there is a set of empirical trials, the objectives of which are to evaluate the prospective standard and provide feedback before standardization. One of the enduring issues being evaluated during the trials is the reliability of assessments based on SPICE. One element of reliability is the extent to which different teams assessing the same processes produce similar ratings when presented with the same evidence. We present some preliminary results from two assessments conducted during the SPICE trials. In each of these assessments two independent teams performed the same ratings. The results indicate that in general there is at least moderate agreement between the two teams in both cases. When we take into account the severity of disagreement then the extent of agreement between the two teams is almost perfect. Also, our results indicated that interrater agreement is not the same for different SPICE processes. The findings reported in this paper provide guidance for future studies of interrater agreement in the SPICE trials and also indicate some potential issues that need to be considered within the prospective standard.

Energy recovery for the design of high-speed, low-power static RAMs

Abstract: We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-recovery SRAM was evaluated through SPICE simulations and compared with a standard design. Simulation results of a 256 × 256 memory configuration indicate that, for successive write operations, energy saving for the different SRAM functions vary from 59% to 76% at 200 MHz operating frequency compared to the conventional design.

Characterization of layout dependent thermal coupling in SOI CMOS current mirrors

Abstract: A current mirror is proposed as a suitable structure for the characterization of layout dependent thermal coupling between MOSFETs. Using current and voltage measurements, and compensating for series resistance effects, very small changes in local device temperature can be made visible. For the first time it is demonstrated that thermal coupling can be observed in a 2 /spl mu/m SOI CMOS technology, with devices separated by as much as 20 /spl mu/m. Measurements were verified by electro-thermal SPICE simulations, using a simple lumped model to express thermal coupling. The observations reinforce the need for accurate circuit level models, including self heating and thermal coupling effects, for analogue applications in VLSI SOI CMOS technologies.

Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits

Abstract: The performance of a CMOS circuit depends heavily on its transistor sizes. We have tested a standard optimizer, a Monte Carlo scheme and a method based on Genetic Algorithms combined with very accurate SPICE simulations to automatically optimize transistor sizes of three different digital CMOS circuits. While the standard optimizer and the Monte Carlo scheme are advantageous for small circuits, the method based on Genetic Algorithms was found to be more stable for larger circuits.

SPICE modeling of power PiN diode using asymptotic waveform evaluation

Abstract: A new power diode model is developed and implemented as a PSPICE subcircuit. The starting point of the new model is a continued-fraction expression in the Laplace domain of the carrier distribution in the base region. By truncating the continued-fraction expansion, lumped RC representations of the base region are easily obtained. In the time domain, this approach approximates of the exact behavior of the carrier distribution with a sum of decaying exponentials, obtained by matching the moments of the exact carrier distribution. The proposed model takes into account emitter recombination in the highly doped end regions, conductivity modulation in the base and the moving-boundaries effect during reverse-recovery, showing good convergence properties and fast simulation times. Comparisons between the results of the SPICE models and numerical device simulations are presented.

Low voltage and low frequency current mirror using a two-MOS subthreshold op amp

Abstract: The authors describe a novel current mirror for low voltage and low frequency application, which uses an op amp with only two MOS transistors operating in the weak inversion region. The advantages of the circuit are low voltage operation, small chip area, high output resistance and no bias current (voltage). The proposed circuit is confirmed by SPICE simulation.

A power modeling and characterization method for the CMOS standard cell library

Abstract: In this paper, we propose power consumption models for complex gates and transmission gates, which are extended from the model of basic gates proposed in Lin et al., (1994). We also describe an accurate power characterization method for CMOS standard cell libraries which accounts for the effects of input slew rate, output loading, and logic state dependencies. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power, and dynamic power. For each component, power equation is derived from SPICE simulation results where the netlist is extracted from cell's layout. Experimental results on a set of ISCAS'85 benchmark circuits show that the power estimation based on our power modeling and characterization provides within 7% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.

A SPICE compatible behavioral model of SEPIC converters

Abstract: An average model of SEPIC power converters operating in continuous current mode (CCM) was developed and verified against cycle-by-cycle simulation. The proposed model is compatible with SPICE and other modern electronic circuit simulators and can be used to run DC (static transfer function), AC (small signal, frequency domain) and TRAN (large signal, time domain) analyses. The model is developed in terms of the average, large signal behavior while the small signal (AC) response is worked out automatically by the simulator. An extension to current programmed SEPIC for the case of peak current mode (PCM) control is also presented. This paper treats the case of SEPIC with uncoupled inductors.

Method and apparatus for automatically characterizing short circuit current and power consumption in a digital circuit

Abstract: Short-circuit current and power consumption for an integrated circuit may be calculated by measuring short-circuit current for various cells within an integrated circuit using a Verilog™ logic level model of the cell. Each cell within an integrated circuit may be characterized by its inputs and outputs and connectivity. A corresponding SPICE sub-circuit model having the same logic characteristics as the cell may be generated. A number of calculation passes are made for each sub-circuit within a cell to determine short circuit current for each sub-circuit at various signal rise and fall times and for various inputs and outputs. Current data may be stored in a format compatible with Verilog™ propagation delay data. Overall power consumption and short circuit current for an integrated circuit may then be calculated from Verilog™ logic model data. The use of the Verilog™ model eliminates the need to calculate short circuit current at a SPICE circuit level. Moreover, putting short circuit data into a propagation delay format allows software to more readily process short circuit data.

Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices

Abstract: This paper presents an accurate model for the evaluation of the CMOS short-circuit power dissipation for short-channel devices, on the basis of a CMOS inverter. The improvement of the proposed approach against previous works is due to the new derived, accurate, analytical expressions for the inverter output waveform which include for the first time the influences of both transistor currents, and the gate-to-drain coupling capacitance. The results produced by she suggested model show good agreement with SPICE simulations.

Continuous HEMT model for SPICE

Abstract: An HEMT model, suitable for SPICE, combines the linear, saturation, and subthreshold modes with a single smooth description. The new model features high order continuity for accurate prediction of current-voltage characteristics, gain, and distortion. This is demonstrated by comparison with measurement.