Showing papers on "Voltage-controlled oscillator published in 2007"

The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking

Abstract: We show that the quadrature LC oscillator is best treated as two strongly coupled, nominally identical oscillators that are locked to the same frequency. Differential equations that extend Adler's description of locking to strong injection reveal the full dynamics of this circuit. With a simplifying insight, the analysis reveals all the modes of the oscillator, their stability, the effects of mismatch on quadrature phase accuracy, and through a novel use of the analysis, phase noise.

A Highly Integrated 60GHz CMOS Front-End Receiver

Abstract: A 60GHz CMOS front-end receiver is described. The receiver comprises an LNA, a quadrature-balanced downconversion mixer, a VCO, and a frequency doubler. The integrated front-end has a conversion gain of 11.8dB, an NF of 10.4dB, and an input P1dB of -15.8dBm. The receiver is implemented in a digital 0.13mum CMOS process and draws 64mA from a 1.2V supply.

Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS

Abstract: A systematic methodology for layout optimization of active devices for millimeter-wave (mm-wave) application is proposed. A hybrid mm-wave modeling technique was developed to extend the validity of the device compact models up to 100 GHz. These methods resulted in the design of a customized 90 nm device layout which yields an extrapolated of 300 GHz from an intrinsic device . The device is incorporated into a low-power 60 GHz amplifier consuming 10.5 mW, providing 12.2 dB of gain, and an output of 4 dBm. An experimental three-stage 104 GHz tuned amplifier has a measured peak gain of 9.3 dB. Finally, a Colpitts oscillator operating at 104 GHz delivers up to 5 dBm of output power while consuming 6.5 mW.

A dual-band coupled vco

Abstract: In a dual band capable voltage controlled oscillator VCO circuit comprising two voltage controlled oscillator units VCOl, VCO2, the voltage controlled oscillator units VCOl, VCO2 are synchronized and connected via at least two coupled transmission lines TLl, TL2, the transmission lines [TLl, TL2) are arranged to operate according to one of two modes to enable varying a combined inductance of the synchronized oscillator units VCOl, VCO2 and the oscillation frequency for the voltage controlled oscillator circuit VCO.

An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL

Abstract: This paper reports an agile VCO frequency calibration technique and its application on a 10-GHz CMOS integer-N phase-locked loop. The proposed calibration method accomplishes efficient search for an optimum VCO discrete tuning curve among a group of frequency sub-bands. The agility is attributed to a proposed frequency comparison technique which is based on measuring the period difference between two signals. Other mixed-signal circuits are also developed to facilitate this approach. The PLL incorporating the proposed calibration technique is implemented in a 0.18-mum CMOS process. The measured PLL phase noise at 10 GHz is -102 dBc/Hz at 1-MHz offset frequency and the reference spurs are lower than -48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4mus

Transformer-Based Dual-Mode Voltage-Controlled Oscillators

Abstract: In this brief, we propose to use a transformer-based resonator to build a dual-mode oscillator, e.g., a system capable of oscillating at two different frequencies without recurring to switched inductors, switched capacitors, or varactors. The behavior of the resonator configured as a one-port and a two-port network is studied analytically, and the dependence of the quality factor on the design parameters is thoroughly explored. These results, combined with the use of traditional frequency tuning techniques, are applied to the design of a wide-band voltage-controlled oscillator (VCO) that covers the frequency range 3.6-7.8 GHz. The performance of the designed VCO, implemented in a digital 0.13-mum CMOS technology, has been studied by transistor-level and 2.5D electromagnetic simulation (Agilent Momentum). A typical phase noise performance at 1-MHz offset of -104 dBc/Hz has been predicted, while the power consumption ranges from 1 to 8 mW, depending on the VCO configuration

A High-Performance CMOS Voltage-Controlled Oscillator for Ultra-Low-Voltage Operations

Abstract: In this paper, a novel circuit topology of voltage-controlled oscillators (VCOs) suitable for ultra-low-voltage operations is presented. By utilizing the capacitive feedback and the forward-body-bias (FBB) technique, the proposed VCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output swing. Using a standard 0.18-mum CMOS process, a 5.6-GHz VCO is designed and fabricated for demonstration. Consuming a dc power of 3 mW from a 0.6-V supply voltage, the VCO exhibits a frequency tuning range of 8.1% and a phase noise of -118 dBc/Hz at 1-MHz offset frequency. With an FBB for the cross-coupled transistors, the fabricated circuit can operate at a supply voltage as low as 0.4 V. The measured tuning range and phase noise are 6.4% and -114 dBc/Hz, respectively

RF and Microwave Transistor Oscillator Design

Abstract: About the Author. Preface. Acknowledgements. 1 Nonlinear circuit design methods. 1.1 Spectral-domain analysis. 1.2 Time-domain analysis. 1.3 Newton-Raphson algorithm. 1.4 Quasilinear method. 1.5 Van der Pol method. 1.6 Computer-aided analysis and design. References. 2 Oscillator operation and design principles. 2.1 Steady-state operation mode. 2.2 Start-up conditions. 2.3 Oscillator configurations and historical aspects. 2.4 Self-bias condition. 2.5 Oscillator analysis using matrix techniques. 2.6 Dual transistor oscillators. 2.7 Transmission-line oscillator. 2.8 Push-push oscillator. 2.9 Triple-push oscillator. 2.10 Oscillator with delay line. References. 3 Stability of self-oscillations. 3.1 Negative-resistance oscillator circuits. 3.2 General single-frequency stability condition. 3.3 Single-resonant circuit oscillators. 3.4 Double-resonant circuit oscillator. 3.5 Stability of multi-resonant circuits. 3.6 Phase plane method. 3.7 Nyquist stability criterion. 3.8 Start-up and stability. References. 4 Optimum design and circuit technique. 4.1 Empirical optimum design approach. 4.2 Analytic optimum design approach. 4.3 Parallel feedback oscillators. 4.4 Series feedback bipolar oscillators. 4.5 Series feedback MESFET oscillators. 4.6 High-efficiency design technique. 4.7 Practical oscillator schematics. References. 5 Noise in oscillators. 5.1 Noise figure. 5.2 Flicker noise. 5.3 Active device noise modelling. 5.4 Oscillator noise spectrum: linear model. 5.5 Oscillator noise spectrum: nonlinear model. 5.6 Loaded quality factor. 5.7 Amplitude-to-phase conversion. 5.8 Oscillator pulling figure. References. 6 Varactor and oscillator frequency tuning. 6.1 Varactor modelling. 6.2 Varactor nonlinearity. 6.3 Frequency modulation. 6.4 Anti-series varactor pair. 6.5 Tuning linearity. 6.6 Reactance compensation technique. 6.7 Practical VCO schematics. References. 7 CMOS voltage-controlled oscillators. 7.1 MOS varactor. 7.2 Phase noise. 7.3 Flicker noise. 7.4 Tank inductor. 7.5 Circuit design concepts and technique. 7.6 Implementation technology issues. 7.7 Practical schematics of CMOS VCOs. References. 8 Wideband voltage-controlled oscillators. 8.1 Main requirements. 8.2 Single-resonant circuits with lumped elements. 8.3 Double-resonant circuit with lumped elements. 8.4 Transmission line circuit realization. 8.5 VCO circuit design aspects. 8.6 Wideband nonlinear design. 8.7 Dual mode varactor tuning. 8.8 Practical RF and microwave wideband VCOs. References. 9 Noise reduction techniques. 9.1 Resonant circuit design technique. 9.2 Low-frequency loading and feedback optimization. 9.3 Filtering technique. 9.4 Noise-shifting technique. 9.5 Impedance noise matching. 9.6 Nonlinear feedback loop noise suppression. References. Index.

Oscillator comprising foldover detection

Abstract: Control circuitry is disclosed including an oscillator operable to generate an oscillator signal. A frequency of the oscillator signal increases as an amplitude of a first voltage increases up to a threshold, and the frequency of the oscillator signal decreases as an amplitude of the first voltage exceeds the threshold. The oscillator is operable to generate a foldover signal indicating when the frequency of the oscillator signal is decreasing due to the first voltage exceeding the threshold.

Design of Wide-Tuning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture

Abstract: The design of a wide-tuning-range millimeter-wave CMOS VCO is presented in this paper. In contrast to the conventional wideband topologies, a nonuniform standing-wave oscillator utilizing tapered gain elements, switched transmission lines and distributed varactors is employed to provide an extended output range with the coarse and fine frequency tuning. Due to the use of the transmission line architecture and the position-dependent amplitude of the standing waves, the loading effects of the varactors and the MOS switches can be alleviated, enabling the VCO to operate at higher frequencies. Using a 0.18-mum CMOS process, a 40-GHz VCO is designed and implemented. Consuming a DC power of 27 mW from a 1.5-V supply voltage, the fabricated circuit exhibits a frequency tuning range of 7.5 GHz with an output power level ranging from -13.6 to -4 dBm. The measured phase noise at 1-MHz offset is lower than -96 dBc/Hz within the entire frequency range. This work demonstrates the widest tuning range in percentage among the CMOS VCOs at millimeter-wave frequencies.

A 50-GHz Phase-Locked Loop in 0.13- $\mu$ m CMOS

Abstract: A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.

Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size

Abstract: As the tuning range of integrated LC-VCOs increases, it becomes difficult to co-design the active negative resistance core and the varactor size optimally for the complete frequency range. The presented VCO design solves this by adjusting the size of the negative resistance transistors with a switched active core, with the additional benefit that this reduces parasitics and hence allows to achieve better phase noise and an even higher tuning range. Also the VCO gain variations are counteracted by employing an analog varactor that can change in size. The implementation in 0.13-mum CMOS shows a tuning range from 3.1 to 5.2 GHz, with a power consumption varying accordingly from 7.7 to 2.1 mA from a 1.2 V supply. The measured phase noise is -118 dBc/Hz at 1 MHz from a 4-GHz carrier.

A 60GHz Low-Power Six-Port Transceiver for Gigabit Software-Defined Transceiver Applications

Abstract: A 60GHz six-port transceiver IC in a standard-bulk 0.13mum CMOS process is reported. This chip is composed of a VCO, a modified reflection-type I/Q modulator, a buffer amplifier, an SPDT switch, an LNA, and a six-port detector. The measured results show 4.5dB conversion gain and 4Gb/s modulation BW with 97.7mW DC power consumption.

A 1-V 17-GHz 5-mW CMOS Quadrature VCO Based on Transformer Coupling

Abstract: A 1-V 17-GHz 5-mW quadrature voltage-controlled oscillator (QVCO) based on transformer coupling is presented. Transformer coupling between two LC tank oscillators is proposed to achieve quadrature outputs with improved performance in terms of high frequency, wide tuning range, low phase noise, and low power as compared to existing active-coupling QVCOs. Implemented in a 0.18-mum CMOS process, the proposed QVCO measures a frequency tuning range of 16.5% at 17 GHz and phase noise of -110 dBc/Hz at 1 MHz offset while consuming 5 mA from a 1-V power supply and occupying a core area of 0.37 mm2.

A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS

Abstract: A radiation-hardened-by-design phase-locked loop (PLL)-designed and fabricated in 130 nm CMOS-is shown to mitigate single-event transients (SETs). Two-photon-absorption (TPA) laser tests were used to characterize the error signatures of the PLL and to perform single-event upset (SEU) mapping of the PLL sub-components. Results show that a custom, voltage-based charge pump reduces the error response of the PLL over conventional designs by more than two orders of magnitude as measured by the number of erroneous PLL clock pulses following a single-event. Additionally, SEU mapping indicates a 99% reduction in the vulnerable area of the radiation-hardened-by-design (RHBD) charge pump over a conventional design. Furthermore, the TPA experiments highlight the importance of the voltage-controlled oscillator in the overall SET response of the PLL implementing the RHBD charge pump.

40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOS

Abstract: A 40GHz wide-locking-range frequency divider and a low-phase-noise VCO are implemented in 0.18mum CMOS technology. The frequency divider demonstrates a locking range of 10.6GHz with 0dBm input power while the VCO exhibits a phase noise of -108.65dBc/Hz at 1MHz offset. Each of the 2 circuits consumes 6mW from a 1V supply.

A Magnetically Tuned Quadrature Oscillator

Abstract: Continuous frequency tuning by control of the magnetic field of a transformer - capacitor tank, in a selective oscillator, is explored in this work. A quadrature generator is built connecting two identical transformer - capacitor oscillator cells in a feedback loop. The topology itself assures the currents in the transformer windings are aligned in phase, while their relative amplitude determines, via magnetic coupling, oscillators' tank reactance, i.e., oscillation frequency. This paper introduces the idea, analyzes oscillation amplitude, frequency tuning band, phase noise, and phase accuracy, and discusses design and experiments. Prototypes, realized in 65 nm CMOS, employing MOS varactors to further extend operation bandwidth, show the following performances: 3.2 GHz and 7.3 GHz minimum and maximum oscillation frequency, respectively. Phase noise figure of merit of 176.5 dB at 3.2 GHz and 170.5 dB at 6.4 GHz is observed, with 24 mW maximum power consumption and 1.5 maximum deviation from quadrature.

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

Abstract: A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm2

A 15/30- GHz Dual-Band Multiphase Voltage-Controlled Oscillator in 0.18- $\mu$ m CMOS

Abstract: A multiphase oscillator suitable for 15/30-GHz dual-band applications is presented. In the circuit implementation, the 15-GHz half-quadrature voltage-controlled oscillator (VCO) is realized by a rotary traveling-wave oscillator, while frequency doublers are adopted to generate the quadrature output signals at the 30-GHz frequency band. The proposed circuit is fabricated in a standard 0.18-mum CMOS process with a chip area of 1.1times1.0 mm2. Operated at a 2-V supply voltage, the VCO core consumes a dc power of 52 mW. With a frequency tuning range of 250 MHz, the 15-GHz half-quadrature VCO exhibits an output power of -8 dBm and a phase noise of -112 dBc/Hz at 1-MHz offset frequency. The measured power level and phase noise of the 30-GHz quadrature outputs are -16 dBm and -104 dBc/Hz, respectively

Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators

Abstract: Voltage-controlled oscillators (VCOs) have been shown to dominate the single-event transient (SET) response of mixed-signal circuits such as the phase-locked loop (PLL). An analytical model is presented to determine the VCO design parameters and the associated SET vulnerability. Additionally, radiation-hardened-by-design (RHBD) techniques to mitigate SETs in current-starved VCOs are presented. The proposed mitigation techniques reduce the phase displacement in the output of the VCO following a single-event (SE) by approximately 66%. The availability of the analytical model and RHBD techniques will improve the SE performance of VCO and PLL designs to ensure a specified tolerance to SEs.

An Analysis of $1/f^{2}$ Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar Differential-Pair LC Oscillators)

Abstract: This work presents an analysis of phase noise in the 1/f2 region displayed by both single-ended and differential bipolar Colpitts oscillators. Very accurate and rigorous symbolic phase noise expressions are derived, enabling a deeper insight into the major mechanisms of phase noise generation, and providing new tools for design optimization. Phase noise expressions for the cross-coupled differential-pair LC-tank oscillator are derived as well. The theoretical analysis is validated on a 3 GHz differential bipolar Colpitts VCO implemented in a 0.35 mum SiGe process. Measurements show a phase noise of -123 dBc/Hz or less at 1MHz offset frequency from the 2.8-3.1 GHz carrier, for a phase noise figure-of-merit of at least 183 dBc/Hz across the tuning range. A very good agreement between theory, numerical simulations, and measurements is observed

An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback

Abstract: A fully integrated 0.024 mm2 differentially tuned 6-GHz LC-VCO for 6+Gb/s high-speed serial (HSS) links in 90-nm bulk CMOS is presented. It is smaller than any LC-VCO reported to date at this frequency. Its size is comparable with ring oscillators but it has significantly better phase noise. A circuit technique is introduced to dynamically set the common-mode (CM) voltage of the differential varactor control signals equal to the VCO's CM. Compared to other commonly used techniques such as replica biasing, this technique does not dissipate any extra power and it accurately tracks the output common-mode voltage of the VCO during the oscillations. Using a differential control a very wide tuning range from 4.5 GHz to 7.1 GHz (45%) is achieved. The VCO has a measured phase noise of -117.7 dBc/Hz at a 3-MHz offset from a 5.63-GHz carrier while dissipating 14 mW from a 1.6-V supply.

A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS

Abstract: A 58-60.4GHz frequency synthesizer is implemented in a 90nm CMOS process. A VCO with a distributed-LC tank and a current-reuse frequency divider are used. For 60.4GHz, the measured phase noise at 1 MHz and 2MHz offset is -85.1dBc/Hz and -95dBc/Hz, respectively. Including the buffers, the chip consumes 80mW from a 1.2V supply.

Design and Scaling of W-Band SiGe BiCMOS VCOs

Abstract: This paper discusses the design of 77-106 GHz Colpitts VCOs fabricated in two generations of SiGe BiCMOS technology, with MOS and HBT varactors, and with integrated inductors. Based on a study of the optimal biasing conditions for minimum phase noise, it is shown that VCOs can be used to monitor the mm-wave noise performance of SiGe HBTs. Measurements show a 106 GHz VCO operating from 2.5 V with phase noise of -101.3 dBc/Hz at 1 MHz offset, which delivers +2.5 dBm of differential output power at 25degC, with operation verified up to 125degC. A BiCMOS VCO with a differential MOS-HBT cascode output buffer using 130 nm MOSFETs delivers +10.5 dBm of output power at 87 GHz.

Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits

Abstract: An integrated circuit is used to monitor and process parametric variations, such as temperature and voltage variations. An integrated circuit may include a temperature-sensitive oscillator circuit and a temperature-insensitive oscillator circuit, and frequency difference between the two sources may be monitored. In some embodiments, a parametric-insensitive reference oscillator is used as a reference to measure frequency performance of a second oscillator wherein the second oscillator performance is parametric-sensitive. The measured frequency performance is then compared to a tamper threshold and the result of the comparison is indicative of tampering.

Frequency Switching in Dual-Resonance Oscillators

Abstract: An oscillator with a high-order (>2) resonator has multiple stable modes of oscillations. The stable modes for one such oscillator, having a fourth-order resonator, are found using a nonlinear analysis. By using a proper nonlinear active topology and tank component values, the fourth-order oscillator can generate either of the two distinct frequencies f1 or f2. A method is introduced to dynamically switch between the stable modes of oscillations. It is shown that the phase noise of this fourth-order oscillator, when generating only one of its resonant frequencies, is comparable to the phase noise of a second-order oscillator using the same active topology and resonator quality factor. Furthermore, the fourth-order oscillator has better phase noise and/or higher tuning range in VCO implementations compared to the commonly used switched resonator oscillators. The claims have been verified experimentally through an integrated oscillator prototype with f1 = 2.4 GHz and f2 = 4.7 GHz fabricated in a standard 0.18 mum CMOS technology. The oscillator draws 1.89 mA current of 1.8 V supply. The 1 MHz offset phase noises of the fourth-order oscillator for f1 = 2.4 GHz and f2 = 4.7 GHz are -122.4 dBc/Hz and -123.4 dBc/Hz, respectively.

A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS

Abstract: A complementary LC-VCO is integrated in a 65nm SOI process and is statistically characterized on a 300mm wafer. Average center frequency is 67.9GHz and frequency tuning range is 6.14GHz or 9.05%. It achieves a phase noise of -106dBc/Hz at 10MHz offset and consumes 5.37mW from a 1.2V supply. The VCO yield is 94.7% for 70GHz operation.

5-GHz Low Power Current-Reused Balanced CMOS Differential Armstrong VCOs

Abstract: This letter proposes 5-GHz low power differential Armstrong voltage controlled oscillators (VCOs) based on balanced topology. One designed VCO uses two single-ended Armstrong VCOs coupled to each other in parallel by balanced structure. The other current-reused VCO uses two single-ended Armstrong VCOs stacked in series. The former VCO oscillates from 4.96 to 5.34GHz and the power consumption is 3.9mW at 0.6-V supply voltage. The latter operates from 4.98 to 5.45GHz and dissipates 2.59mW at 1.8-V supply voltage. The measured phase noises are about -116.71dBc/Hz and -110.02dBc/Hz at 1-MHz offset frequency from 5.1-GHz band, respectively. The former and the latter VCO have an advantage of low power consumption and provide a good figure of merit of about -185dBc/Hz and -180dBc/Hz, respectively

System and method for monitoring reliability of a digital system

Abstract: System and method are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades past a specified threshold. The technique includes implementing a ring oscillator sensor in association with the digital system, wherein logic and/or device percent composition of the ring oscillator sensor mirrors percent composition thereof within the digital system. Counter logic is coupled to the ring oscillator sensor for converting outputted count signals to an oscillation frequency, and control logic is coupled to the counter logic for periodically evaluating oscillation frequency of the ring oscillator sensor and generating a warning signal indicative of reliability degradation if at least one of: (i) a measured or estimated oscillation frequency is below a warning threshold frequency; or (ii) a measured or estimated rate of change in a difference between measured oscillation frequencies exceeds an acceptable rate of change threshold.

Design of Adaptive Multimode RF Front-End Circuits

Abstract: Migration towards higher data rates and higher capacities for multimedia applications, and provision of various services (text, audio, video) from different wireless standards with the same device require integrated designs that work across multiple standards, can easily be reused, and achieve maximum hardware share at minimum power consumption. This can be achieved by using adaptive circuits that are able to trade off power consumption for performance. The design of an adaptive multimode image-reject downconverter (oscillator and two mixers) is presented in this paper. In the highest performance mode, the image-reject downconverter (the quadrature mixers) has an IIP3 of +5.5 dBm, a single-side band noise figure of 13.9dB and a conversion gain of 1.4 dB, while drawing 10mA from a 3 V supply. The adaptive oscillator achieves -123 dBc/Hz phase noise at 1MHz offset from a 2.1 GHz carrier with a bias current of 6 mA in the highest performance mode. Adaptivity in the downconverter is achieved by trading off RF performance for current consumption, ranging from 10 mA for the relaxed mode (e.g., DECT) to 20 mA in the highest performance mode (e.g., DCS1800) of operation