Showing papers on "Voltage-controlled oscillator published in 2019"

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS

Abstract: This paper reports an ultralow-voltage (ULV) energy-harvesting bluetooth low-energy (BLE) transmitter (TX). It features: 1) a fully integrated micropower manager ( $\mu $ PM) to customize the internal supply and bias voltages for both active and sleep modes; 2) a gate-to-source-coupling ULV voltage-controlled oscillator (VCO) using a high-ratio (5.6:1) stacking transformer to improve the phase noise and output swing; 3) an ULV class-E/F2 power amplifier (PA) with an inside-transformer LC notch to suppress the HD3, and finally 4) an analog type-I phase-locked loop (PLL) with a reduced duty cycle of its master-slave sampling filter (MSSF) to suppress the jitter and reference spur. The TX prototyped in 28-nm CMOS occupies an active area of 0.53 mm2 and exhibits 25% system efficiency at 0-dBm output at a single 0.2-V supply. Without resorting from any external components, both the output HD2–49.6 dBm) and HD3–47.4 dBm) comply with the BLE standard. The FSK error is 2.84% and the frequency drift in a 425- $\mu \text{s}$ data packet is <5 kHz under open-loop modulation. The use of negative-voltage power gating suppresses the sleep power of the entire TX to 5.2 nW.

26.3 A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios

Abstract: Because of their promise of wide bandwidths and high data-rates, fifth-generation (5G) wireless systems are expected to be deployed worldwide over the next decade. Several bands in the 25-to-40GHz range are allocated for 5G radios. A single widely tunable LC VCO covering the required bands is difficult to design, but is more compact than a set of multiple narrowly tuned VCOs, and is, therefore, preferred. In practice, it is difficult to simultaneously achieve low phase noise and wide tuning range by varying only the capacitor in an LC VCO because (a) switchable capacitor banks have a poor quality factor, Q, at millimeter-wave frequencies and degrade the phase noise, and (b) using wide switches to increase Q increases parasitics and reduces the tuning range.

A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface

Abstract: The bidirectional neural interface is essential to realize the closed-loop neuromodulation, which is the core of next-generation neurological devices. For the bidirectional neural interface, a recording circuit with a high dynamic range (DR) is required to record the neural signal while stimulating the neuronal cells simultaneously. This article presents a voltage-controlled oscillator (VCO)-based neural-recording IC, which directly quantizes the input signal and achieves a large DR to process the small-amplitude neural signal in the presence of the large-amplitude stimulation artifact (SA). A feedback-controlled source degeneration is applied to the input transconductor circuit ( $G_{\mathrm {m, in}}$ ) by using a resistor digital-to-analog converter (R-DAC). It mitigates the circuit nonlinearity, resulting in a large signal-to-noise-and-distortion ratio (SNDR) and a high input impedance ( $Z_{\mathrm {in}}$ ). The implemented neural-recording IC achieves 81.3-dB SNDR over 200-Hz signal bandwidth and 200-mVpp maximum allowable input range with consuming 3.9 $\mu \text{W}$ per channel. The in-vitro measurement with prerecorded neural signal demonstrates that the original neural signal is well preserved in the presence of the large-amplitude artifact without any saturation or significant distortion.

A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

Abstract: Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-locked clock multipliers have demonstrated some of the lowest jitters for a given power consumption (jitter-power ${\text {FoM}}_{j}$ metric). However, they contain a tradeoff between the spur and noise performance, where techniques incorporated for spur reduction adversely affect jitter or power performance. A new dividerless Type-I sampling PLL, called the reference sampling PLL (RS-PLL), which estimates the voltage-controlled oscillator (VCO) phase error by sampling the reference sine wave with a VCO square wave is demonstrated. A clock-and-isolation buffer which accelerates the VCO sine wave to a square wave sampling clock and simultaneously isolates the VCO tank from spur mechanisms in the sampler is included in place of a traditional reference buffer. By combining sampling clock buffer and VCO isolation functionalities into a single block, the RS-PLL eliminates the noise penalty of two separate buffers. The power penalty due to sampling at VCO frequency is restricted by limiting the activity of the switching circuits to the region around the reference zero crossing where the phase error information exists. The prototype RS-PLL implemented in 65-nm CMOS achieves a jitter-power ${\text {FoM}}_{j}$ of <−251 dB between 2.05 and 2.55 GHz with a reference spur of <−66 dBc at 50 MHz. In doing so, it improves upon the simultaneous noise and spur performance achieved by current state-of-the-art clock multipliers.

16.2 A 76fs rms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

Abstract: The generation of mm-wave (mmW) signals that have ultra-low phase noise (PN) is very important for the design of RF transceivers (TRXs) for high-data-rate 5G systems. Direct-RF-sampling TRXs also require high-frequency clock signals, having extremely low integrated PN (IPN) [1]. To satisfy such stringent noise requirements, the rms jitter of mmW-band signals must be reduced to sub-100fs. Recently, a charge-pump (CP) PLL in [1] achieved a very low rms jitter of less than 60fs at 14GHz. However, to suppress the in-band PN of PLL building blocks, that design used a reference clock that had an impractically high frequency, $f_{\mathrm{REF}}$, of 500MHz. To avoid the use of such a high $f_{\mathrm{REF}}$ while minimizing in-band PN, sub-sampling PLLs (SSPLLs) are seen as a promising solution. However, conventional SSPLLs are not suitable for generating mmW-band signals directly, since, as the frequency increases, the capture range of their sampling operation is reduced rapidly, thereby hindering the reliable operation. To extend the capture range, a prescaler can be used after the VCO [2], but it increases the in-band PN and power consumption. Direct-mmW SSPLLs are limited even at suppressing out-of-band PN, since their PN skirt is determined by an mmW VCO that has a relatively low Q. To overcome the problems of analog SSPLLs, such as a large area and a PVT-sensitive loop gain, digital SSPLLs using ADCs to digitize the sampled voltage have been developed recently [3]. However, digital SSPLLs suffer from another problem in that, to reduce the quantization noise (Q-noise) and improve the overall IPN, they must use high-performance ADCs that concurrently have high-sampling frequencies, fine resolutions, and wide dynamic ranges. Thus, they demand high power and occupy larger area.

A Noise Circulating Oscillator

Abstract: This paper presents a noise circulating cross-coupled voltage-controlled oscillator (VCO) topology with a transformer-based tank. The introduced noise circulating active core greatly suppresses the effective noise power from the active devices while offering the same amount of negative resistance compared to conventional cross-coupled VCO topologies. The mechanism of noise circulation is investigated with theoretical analysis and further verified by simulation. Due to the broadband nature of the noise circulating technique, the resulting VCO phase noise in both 1/ $f^{2}$ and 1/ $f^{3}$ regions is greatly improved over a wide frequency tuning range. A prototype VCO at 2.35 GHz is implemented in a standard 130-nm bulk CMOS process with 0.36-mm2 core area. It draws 2.15 mA from a 1.2-V supply. The measured figure-of-merit (FoM) is 193.1/195.0/195.6 dBc/Hz at 100k/1M/10MHz offsets with a 1/ $f^{3}$ phase noise corner of only 50 kHz. The VCO design consistently achieves >192.8 dBc/Hz FoM at 100k/1M/10MHz offsets and $f^{3}$ phase noise corner over its entire 18.6% frequency tuning range (2.05 − 2.47 GHz). It also exhibits low supply frequency pushing of −25 and −13 MHz/V at the highest and lowest frequencies, respectively.

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- $\mu$ m CMOS

Abstract: This brief presents a 10-bit 5 MS/s hybrid analog-to-digital converter (ADC) combining successive approximation register (SAR) with voltage-controlled oscillator (VCO) in 0.18- $\mu \text{m}$ CMOS. Non-ideal factors from practical circuit implementations are theoretically considered and modeled in Simulink. To improve the linearity and the reliability of the bootstrapped switch circuit, the body-effect compensation is adopted. The asynchronous clock generation circuit with a variable-time control cell is presented, which optimizes the DAC settling time of the MSB DAC and LSB DAC in an SAR conversion. Verilog codes and a standard digital library make it possible to synthesize the most parts of the VCO-based Nyquist ADC, greatly reducing the design costs. At Nyquist input frequency and a 5 MS/s sampling rate, a signal-to-noise and distortion ratio of 56.7 dB and a spurious-free dynamic range of 72.2 dB are achieved, respectively. The core occupies $450\,\, {\mu }{ \text{m}} {\times } {280}\,\, {\mu }\text{m}$ .

A Highly Integrated D-Band Multi-Channel Transceiver Chip for Radar Applications

Abstract: This paper presents a low-power, highly-integrated D-Band transceiver chip realized in a 0.13 µm SiGe BiCMOS technology. The integration level includes three receiver (RX) channels, one transmitter (TX) channel, local oscillator (LO) signal generation and distribution network, frequency dividers and serial peripheral interface (SPI) for digital reconfigurability. The receiver achieves a peak gain of 14 dB at 118 GHz, while the transmitter achieves an output power of −6 dBm at 118 GHz. The VCO is realized in a push-push Colpitts topology. Additionally, its output is multiplied by two using a frequency doubler. Hence the transmitter output signal is continuously tunable in the frequency range 117 − 126 GHz, while achieving a measured phase noise of − 93.5 dBc /Hz at 1 MHz offset at 120 GHz. The entire transceiver draws 195 mA from a single 1.8 V supply. A single RX channel draws 19 mA, while a single TX consumes 25 mA. The circuit including pads occupies a chip area of only 3.5 mm × 2.75 mm, which is limited only by the separation necessary for isolation between the channels. The transceiver provides a competitive performance and is suitable for continuous-wave radar applications around 120 GHz.

A 2.3-mW 26.3-GHz $G_{m}$ -Boosted Differential Colpitts VCO With 20% Tuning Range in 65-nm CMOS

Abstract: This paper presents an architecture for differential Colpitts voltage-controlled oscillators (VCOs) in complementary metal–oxide–semiconductor (CMOS) that utilizes three design techniques to extend the tuning range (TR) of the VCO, while maintaining a low phase noise (PN) and a low power consumption. First, a switched-capacitor bank based on a variable capacitive feedback technique is introduced to achieve a wide TR with a minimal PN degradation. Second, a $G_{m}$ -boosting technique using interstage inductors is employed to lower the power consumption and relax VCO startup issues. Third, a dynamic forward-body self-biased technique is used to further reduce the power consumption and PN of the proposed structure. As a proof of concept, a 26.3-GHz differential Colpitts VCO is designed and fabricated in a 65-nm CMOS process. Based on the measurement results, the VCO achieves a PN of −122.1 dBc/Hz at 10-MHz offset from the center frequency, and a TR of 20%. The circuit consumes 2.3 mW from a 1-V supply and excluding the pads occupies a 0.22 mm2 of silicon area. Compared to the recently published CMOS VCOs within the same frequency range, the proposed VCO simultaneously achieves a wide TR, low power dissipation, and low PN, resulting in a figure of merit (FOM) and FOM incorporating the TR (FOM $_{T}$ ) of −187 and −193 dBc/Hz at 10-MHz offset from the center frequency, respectively.

A 0.025-mm 2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure

Abstract: This paper presents a capacitive-coupled VCO-based sensor readout featuring a hybrid PLL $- \Delta \Sigma \mathrm {M}$ structure. It leverages phase-locking and PFD array to concurrently perform quantization and DEM, much reducing hardware/power compared to existing VCO-based readouts counting scheme. A low-cost in-cell DWA scheme is presented to enable highly linear tri-level DAC. Fabricated in 40nm CMOS, the prototype readout achieves 78dB SNDR in 10kHz BW, consuming $4.5 \mu \mathrm {W}$ and 0.025mm2 active area. With 172dB Schreier FoM, its efficiency advances state-of-the-art VCO-based readouts by $50 \times $.

A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator is presented in this paper. The relationship between the input voltage and the number of oscillation cycles (NOC) to reach a VCO-comparator decision is explored, implying an inherent coarse quantization in parallel with the normal comparison. The NOC as a design parameter is introduced and analyzed with noise, metastability, and tradeoff considerations. The NOC is exploited to bypass a certain number of SAR cycles for higher power efficiency of VCO-based SAR ADCs. To cope with the process, voltage, and temperature (PVT) variations, an adaptive bypassing technique is proposed, tracking and correcting window sizes in the background. Fabricated in a 40-nm CMOS process, the ADC achieves a peak effective number of bits of 9.71 b at 10 MS/s. Walden figure of merit (FoM) of 2.4–6.85 fJ/conv.-step is obtained over a wide range of supply voltages and sampling rates. Measurement has been carried out under typical, fast-fast, and slow-slow process corners and 0 °C–100 °C temperature range, showing that the proposed ADC is robust over PVT variations without any off-chip calibration or tuning.

A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output Voltage Range

Abstract: The controller of a current-mode buck converter is realized by only time-domain circuits such as voltage-controlled oscillator (VCO), voltage-controlled delay line (VCDL), and phase detector (PD). The inductor current is sensed by a VCO, which helps improving power efficiency and eliminates the need for the slope compensation preventing the sub-harmonic oscillation. The type-II frequency compensation network is realized by a combination of VCO and VCDL without an error amplifier (EA) and RC network which may consume large power and occupy large silicon area. Instead of voltage comparator, a PD detects the error of the output voltage, which allows the switching duty cycle and thus the output voltage to be controlled in a wide range. With the proposed time-domain current-mode controller, a buck converter has been implemented in a 65-nm CMOS process. The output voltage can be regulated from 0.15 to 1.69 V from a 1.8-V input and the maximum load current is 0.6 A. The peak power efficiency is 94.9% when the output is 1.5 V and the load current is 250 mA. The load transient speed is better than 3.5 $\mu \text{s}$ for both the step-up and step-down changes of the load current by 480 mA in 0.1 $\mu \text{s}$ .

A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing

Abstract: This paper introduces a voltage-controlled oscillator (VCO)-based nonuniform sampling (NUS) analog-to-digital converter (ADC), which shifts the conventional voltage-domain level crossing to the phase domain, thus eliminating the need for any continuous-time (CT) comparator or reference generator. It increases the signal bandwidth and reduces the implementation costs of both analog and digital circuitries compared to the existing voltage-domain NUS ADCs. The signal-to-quantization-noise ratio (SQNR) is improved by the first-order noise shaping and inherent dithering via the free-running oscillation of VCO. The quantization error of the proposed architecture is analyzed, and a phase-domain calibration on the VCO nonlinearity is proposed. Due to the mostly digital architecture and time-based nature of the proposed architecture, the performance and figure of merit (FOM) are expected to improve with the scaled technology. This prototype achieves 200-MHz bandwidth with 60-dB dynamic range (DR) and consumes 19.7 mW of power with an active area of 0.13 mm2 in 65-nm complementary metal–oxide–semiconductor (CMOS), where the nonuniform digital signal processing (DSP) is performed off chip. The estimated power and area of the nonuniform DSP including the calibration and decimation filter are 30 mW and 0.114 mm2, respectively.

A Wide Tuning Range, Low Phase Noise, and Area Efficient Dual-Band Millimeter-Wave CMOS VCO Based on Switching Cores

Abstract: This paper presents a millimeter-wave wide tuning range voltage-controlled oscillator (VCO) incorporating two switchable decoupled VCO cores. When the first core is switched on producing the low frequency band (LFB) signal and the second core is off, the inductors of the second core are reused to create additional buffers that pass the LFB signal to the output buffers. The generated high frequency band (HFB) signals by the second core when turned on, are directly fed to the output buffers. Producing the outputs of both VCO cores across same terminals without utilizing active/passive combiners and coupled inductors will enhance the phase noise performance of the VCO, increase its output power, and reduce the chip size. Fabricated in a 65-nm CMOS process, the VCO achieves a measured wide tuning range of 26.2% from 54.1 to 70.4 GHz while consuming 7.4–11.2-mA current from 1-V power supply. The peak measured phase noise at 10-MHz offset is −116.3 dBc/Hz and the corresponding FOMT and FOM varies from −180.96 to −191.86 dB and −172.6 to −183.5 dB, respectively. The VCO core area occupies only $0.1 \,\, \times 0.395\,\,\mu \text{m}^{{2}}$ .

A Ka Band FMCW Transceiver Front-End With 2-GHz Bandwidth in 65-nm CMOS

Abstract: A fully integrated Ka band frequency modulation continuous wave single-chip radar transceiver front-end is proposed in 65-nm CMOS technology. By utilizing VCO with multi-biasing varactor banks, the critical bandwidth and linearity have been improved. To address the challenges of losses and complexities in local oscillator (LO) distribution chain, a three-way transformer-based power divider is proposed and implemented to split the input differential signals to three outputs, in three orthogonal directions. The poly phase filter is also used to obtain the in-phase and quadrature LO signals. To minimize the reflections between the poly phase filter and the following stages, a 1:2 transformer is inserted to provide sufficient matching. For the receiver part, differential cascode amplifier with neutralization capacitors is implemented in the low noise amplifier to obtain gain and stability. By utilizing double balanced passive mixers, noise performances of I/Q paths are improved at low intermediate frequency. The transceiver demonstrates 4.4-dBm output power, 2-GHz bandwidth with 7.5-cm range resolution, and 5.9–7.5 dB double side band noise figure at 4 MHz. The whole transceiver front-end consumes 132 mW from 1.2 V and 2.16 mm2 die size.

A Scalable Four-Channel Frequency-Division Multiplexing MIMO Radar Utilizing Single-Sideband Delta–Sigma Modulation

Abstract: A scalable four-channel multiple-input multiple-output (MIMO) radar that features a modular system architecture and a novel frequency-division multiplexing approach is presented in this article. It includes a single 30-GHz voltage-controlled oscillator (VCO) for the local oscillator signal generation, four cascaded 120-GHz transceivers with a frequency quadrupler, and on-board differential series-fed patch antennas. The utilized uniform antenna configuration results in 16 virtual array elements and enables an angular resolution of 6.2°. The vector modulators in the transmit (TX) paths allow the application of complex bit streams of second-order delta–sigma modulators easily generated on a field-programmable gate array (FPGA) to implement single-sideband (SSB) modulation on the TX signals resulting in orthogonal waveforms for the MIMO operation. Only one phase-locked loop and no digital-to-analog converter is required. The waveform diversity also allows the simultaneous transmission of the TX signals to reduce the measurement time. The application of the SSB modulation on the frequency-modulated continuous-wave MIMO radar requires only half of the intermediate frequency bandwidth compared with the double-sideband modulation. The issue of the phase and amplitude mismatches at the virtual array elements due to the scalable radar architecture is addressed and a calibration solution is introduced in this article. Radar measurements using different numbers of virtual array elements were compared and the digital-beamforming method was applied to the results to create 2-D images.

Enhanced circuit for linear ring VCO-ADCs

Abstract: Recently an extremely linear voltage-controlled ring-oscillator for use in VCO-ADCs was proposed by Babaie-Fishani and Rombouts. In this current Letter, a circuit-level technique to improve the bandwidth and noise performance of such a linear VCO is proposed. The key element is the modified delay cell, where the traditional cross-coupled inverters are modified into ` feed-forward' coupling inverters that pre-charge the subsequent elements in the ring. The resulting circuit maintains the excellent linearity, but has greatly enhanced bandwidth (up to 3 times higher) and considerably reduced power for the same circuit noise level (up to 2.5 times lower).

On the Design of a High-Performance mm-Wave VCO With Switchable Triple-Coupled Transformer

Abstract: In this article, we present a circuit technique to design a wide tuning range (TR) voltage-controlled oscillator (VCO). The employed technique extends the TR with a minimal adverse effect on the phase noise (PN). In this context, a switchable triple-coupled transformer, implemented utilizing the topmost three metal layers of the process, is proposed to achieve a wide TR and a low PN. In the proposed configuration, the mutual coupling between the loads is increased while canceling the negative effects of the switches on the transformer performance. Depending on the possible states of the switches used in the secondary and tertiary coils, four overlapping frequency sub-bands are introduced. An extensive set of analysis is provided to support the idea. As a proof-of-concept, a 55-GHz VCO is implemented in a 65-nm CMOS process. Based on the measurement results, the VCO achieves an average PN of −111.9 dBc/Hz at 10-MHz offset over the entire frequency range and a TR of ~18%, from 50.1 to 59.8 GHz, exhibiting a figure of merit incorporating the TR (FOM $_{T}$ ) of −184 dBc/Hz at 10 MHz. The VCO core consumes 6.2 mW from a 1-V supply and, excluding the pads, occupies a compact silicon area of 0.06 mm2.

A CMOS active inductor based digital and analog dual tuned voltage-controlled oscillator

Abstract: A fully integrated 600 MHz CMOS active inductor based voltage-controlled oscillator (VCO) is presented The active floating inductor configuration employs voltage differencing transconductance amplifier as a building block In the proposed circuit topology, frequency tuning is realized by varying the bias current of the tunable inductor The designed VCO achieves an output frequency of 450–750 MHz, resulting in the tuning range of 50% The simulated phase noise lies within −9237 to −8616 dBc/Hz at 1 MHz offset and the VCO draws 42698–1100 µW from a 1 V supply voltage The proposed RF oscillator is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso Analog Design Environment of Cadence

28-GHz CMOS VCO With Capacitive Splitting and Transformer Feedback Techniques for 5G Communication

Abstract: This paper presents a 28-GHz low phase noise voltage-controlled oscillator (VCO) in a 65-nm CMOS process for 5G communication applications. With the capacitive splitting and transformer feedback techniques, theoretical analysis and simulations are undertaken for the proposed oscillator, proving that its negative $G_{m}$ can be enhanced over the interested frequency range and reduced at the harmonic frequencies. Moreover, the proposed oscillator startup performance is analyzed, and its tank quality factor, transient and phase noise performance are simulated. With 4-bit switch capacitors and varactors, the proposed VCO achieves a tuning range from 25.7 to 29.7 GHz, consuming 10.8 mW from a 0.9-V supply voltage. With a wideband common-source buffer, the output signal power is around 1 dBm. At 26.5 GHz, the proposed VCO achieves low phase noise of −105.8 dBc/Hz at 1-MHz offset and −130 dBc/Hz at the 10-MHz offset, respectively.

Design of CMOS-based low-power high-frequency differential ring VCO

Abstract: An improved design of four-stage CMOS differential ring voltage-controlled oscillator (VCO) with high-output frequency, low phase noise, and low power consumption is proposed in this paper. A new d...

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications

Abstract: In this paper, the performance boundaries and corresponding tradeoffs of a complex dual-mode class-C/D voltage-controlled oscillator (VCO) are extended using a framework for the automatic sizing of radio frequency integrated circuit blocks, where an all-inclusive test bench formulation enhanced with an additional measurement processing system enables the optimization of “everything at once” toward its true optimal tradeoffs. VCOs embedded in the state-of-the-art multistandard transceivers must comply with extremely high performance and ultralow power requirements for modern cellular and Internet of Things applications. However, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from multiple modes, test benches, and/or analysis must be considered simultaneously. Here, the dual-mode design and optimization conducted provided 287 design solutions with figures of merit above 192 dBc/Hz, where the power consumption varies from 0.134 to 1.333 mW, the phase noise at 10 MHz from −133.89 to −142.51 dBc/Hz, and the frequency pushing from 2 to 500 MHz/V, on the worst case of the tuning range. These results pushed this circuit design to its performance limits on a 65-nm CMOS technology, reducing 49% of the power consumption of the original design while also showing its potential for ultralow power with more than 93% reduction. In addition, worst case corner criteria were also performed on the top of the worst case tuning range optimization, taking the problem to a human-untrea table LXVI-D performance space.

Electronic Circuit with Controllable Negative Differential Resistance and its Applications

Abstract: Electronic devices and circuits with negative differential resistance (NDR) are widely used in oscillators, memory devices, frequency multipliers, mixers, etc. Such devices and circuits usually have an N-, S-, or Λ-type current-voltage characteristics. In the known NDR devices and circuits, it is practically impossible to increase the negative resistance without changing the type or the dimensions of transistors. Moreover, some of them have three terminals assuming two power supplies. In this paper, a new NDR circuit that comprises a combination of a field effect transistor (FET) and a simple bipolar junction transistor (BJT) current mirror (CM) with multiple outputs is proposed. A distinctive feature of the proposed circuit is the ability to change the magnitude of the NDR by increasing the number of outputs in the CM. Mathematical expressions are derived to calculate the threshold currents and voltages of the N-type current-voltage characteristics for various types of FET. The calculated current and voltage thresholds are compared with the simulation results. The possible applications of the proposed NDR circuit for designing single-frequency oscillators and voltage-controlled oscillators (VCO) are considered. The designed NDR VCO has a very low level of phase noise and has one of the best values of a standard figure of merit (FOM) among recently published VCOs. The effectiveness of the proposed oscillators is confirmed by the simulation results and the implemented prototype.

20.1 A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step

Abstract: Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs are able to benefit directly from improved digital performance [1]; however, the resolution and sampling rate of state-of-the-art VCO-based designs are insufficient for most applications. This paper presents a faster and more efficient VCO-based ADC architecture based on an improved high-speed, low-power ring oscillator and an asynchronous counting strategy. The architecture is 8× time-interleaved and combined with on-chip calibration. The design is implemented in 28nm CMOS and achieves 45.2dB SNDR (7.2 ENOB) near Nyquist at 5GS/s while consuming only 22.7mW, resulting in a Walden FOM of 30.5fJ/conv-step. The core area is only 0.023mm 2. These results demonstrate that VCO-based ADCs are a viable choice for next-generation Ethernet and high-speed wireless communication.

A 0.0056-mm 2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

Abstract: This paper describes an ultra-compact all-digital multiplying delay-locked loop (MDLL) featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the process–voltage–temperature variations of the voltage-controlled oscillator (VCO) frequency. Such FTL utilizes a digital-controlled delay line (DCDL)-based low-power time-interval comparator and an adjacent-edge selector, to precisely detect the static phase offset (SPO) caused by the VCO frequency drifting in the presence of reference injection. The block-sharing-based SPO detection aids nullifying the circuit-mismatch- and offset-induced deterministic error. Also, for the adjacent edge selector, block sharing between its control generation circuits and the coarse FTL further reduces the power consumption. The varactor-tuned dual multiplexed-ring VCOs (MRVCOs) serve to reduce jitter variation while extending the frequency tuning range. Fabricated in a 28-nm CMOS with a core area of 0.0056 mm2, the proposed MDLL covers a tuning range from 1.55 to 3.35 GHz, and exhibits a root-mean-square (rms) jitter of 292 fs at 3-GHz output, under a 200-MHz reference clock. The power consumption is 1.45 mW at a 0.8-V supply, resulting in an FoM of −249 dB favorably comparable with the state of the art.

An Ultralow Phase Noise Eight-Core Fundamental 62-to-67-GHz VCO in 65-nm CMOS

Abstract: An eight-core fundamental VCO with ultralow phase noise (PN) performance is presented. Eight VCOs are in-phase coupled for low PN, and a 9-dB PN improvement is achieved. A scalable layout methodology is presented to solve the layout difficulties in multicore VCOs. Two VCO cores are connected together directly to form a VCO cell. By simply connecting $N$ /2 VCO cells, the PN of the entire multicore VCO will achieve a 10 logN dB PN improvement compared with the single VCO core. The proposed eight-core VCO is fabricated in 65-nm CMOS and occupies 0.15 mm2. The measured PN is −105.5 dBc/Hz at 1-MHz offset, with the tuning range from 62.2 to 67.3 GHz (7.9%). The VCO consumes 61.2-mW power with the figure-of-merit of −183.5 dBc/Hz at 1-MHz offset.

Mesh Based Obfuscation of Analog Circuit Properties

Abstract: In this paper, a technique to design analog circuits with enhanced security is described. The proposed key based obfuscation technique uses a mesh topology to obfuscate the physical dimensions and the threshold voltage of the transistor. To mitigate the additional overhead of implementing the obfuscated circuitry, a satisfiability modulo theory (SMT) based algorithm is proposed to auto-determine the sizes of the transistors selected for obfuscation such that only a limited set of key values produce the correct circuit functionality. The proposed algorithm and the obfuscation methodology is implemented on an LC tank voltage-controlled oscillator (VCO). The operating frequency of the VCO is masked with a 24-bit encryption key applied to a 2×6 mesh structure that obfuscates the dimensions of each varactor transistor. The probability of determining the correct key is 5.96×10−8 through brute force attack. The dimensions of the obfuscated transistors determined by the analog satisfiability (aSAT) algorithm result in at least a 15%, 3%, and 13% deviation in, respectively, the effective transistor dimensions, target frequency, and voltage amplitude when an incorrect key is applied to the VCO. In addition, only one key produces the desired frequency and properly sets the overall performance specifications of the VCO. The simulated results indicate that the proposed design methodology, which quickly and accurately determines the transistor sizes for obfuscation, produces the target specifications and provides protection for analog circuits against IP piracy and reverse engineering.

A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications

Abstract: This paper describes a bank of four SiGe BiCMOS oscillators tailored to cover the 18.2-29.3 GHz frequency range, needed to tackle the needs of 5G communications. The Colpitts oscillator topology is leveraged to achieve a lower absolute phase noise compared to Class-C oscillators, at the expense of deteriorated figure of merit. Benefiting from the proper technology choice, a careful tank design was carried out to maximize Q, minimize K VCO and phase noise variations. The four oscillators feature state-of-the-art phase noise, ranging from -119.5 dBc/Hz to -116.5 dBc/Hz at 1MHz offset for 18.2 GHz and 29.3 GHz carrier frequency, respectively. For each oscillator the phase noise variation is only <2 dB over -20°C to 85°C temperature range and <6 dB over the whole 47% tuning range.

A −192.7-dBc/Hz FoM $K_{U}$ -Band VCO Using a DGS Resonator With a High-Band Transmission Pole in 0.18- $\mu$ m CMOS Technology

Abstract: This letter presents the improvement of the phase noise (PN) of a voltage-controlled oscillator (VCO) by using a defected ground structure (DGS) resonator with a high-band transmission pole. The proposed DGS resonator has two loops in a coplanar stripline topology. The outer loop is loaded by a series capacitance, which produces the high-band transmission pole. The overall combination has a parallel capacitor to generate the necessary parallel resonance for the VCO operation. This proposed DGS resonator has a sharper impedance and frequency response slope, which results in an improved quality factor. In return, utilization of this DGS resonator into a $K_{U}$ -Band VCO reduces its PN. The prototyped VCO in 0.18- $\mu \text{m}$ CMOS oscillates at 15.52 GHz and shows a PN of −111.27 and −134.07 dBc/Hz at 1- and 10-MHz offset, respectively, while consuming 3.3-mW power. The VCO has a frequency tuning range of 9.5%, which results in a figure of merit (FoM) of −192.7 dB.

A CMOS V-Band PLL With a Harmonic Positive Feedback VCO Leveraging Operation in Triode Region for Phase-Noise Improvement

Abstract: This paper presents a 53–61 GHz low-power charge-pump integer-N type-II PLL, employing a class-D V-band voltage control oscillator. Transistors in the VCO enter deep triode region to achieve low DC power and phase noise. Pros and cons of the triode region are studied in this paper. We have explained how this region has been accurately exploited to reduce the phase-noise. This is unlike the general notion that the triode region degrades phase-noise performance in oscillators. The phase locked loop is fabricated in a standard 65 nm CMOS process. The VCO consumes the minimum power of 10.6 mW from 0.8 V supply. The PLL achieves a wide tuning range of 13% from 53.35–60.83-GHz and a phase noise of −88 dBc/Hz at 1–MHz offset, while consuming a minimum DC power of 48 mW. This PLL can be used as part of the LO generation network for millimeter-wave phased-array transceivers.