Showing papers on "Wafer published in 1999"

Photovoltaic Technology: The Case for Thin-Film Solar Cells

Abstract: The advantages and limitations of photovoltaic solar modules for energy generation are reviewed with their operation principles and physical efficiency limits. Although the main materials currently used or investigated and the associated fabrication technologies are individually described, emphasis is on silicon-based solar cells. Wafer-based crystalline silicon solar modules dominate in terms of production, but amorphous silicon solar cells have the potential to undercut costs owing, for example, to the roll-to-roll production possibilities for modules. Recent developments suggest that thin-film crystalline silicon (especially microcrystalline silicon) is becoming a prime candidate for future photovoltaics.

Projection exposure method and system

Abstract: A projection exposure method capable of keeping a liquid (7) filled between a projection optical system (PL) and a wafer (W) even while the wafer (W) is being moved when a liquid immersion method is used to conduct an exposure, wherein a discharge nozzle (21a) and inflow nozzles (23a, 23b) are disposed so as to hold a lens (4) at the tip end of the projection optical system (PL) in an X direction. When the wafer (W) is moved in a -X direction by an XY stage (10), a liquid (7) controlled to a preset temperature is supplied from a liquid supply device (5) via a supply pipe (21) and the discharge nozzle (21a) so as to fill the portion between the lens (4) and the surface of the wafer (W) and the liquid (7) is recovered from the surface of the wafer (W) by a liquid supply device (6) via a recovery pipe (23) and the inflow nozzles (23a, 23b), the supply amount and recovery amount of the liquid (7) being regulated according to a moving speed of the wafer (W).

Characterization of a Time Multiplexed Inductively Coupled Plasma Etcher

Abstract: We report the experimentally obtained response surfaces of silicon etching rate, aspect ratio dependent etching (ARDE), photoresist etching rate, and anisotropy parameter in a time multiplexed inductively coupled plasma etcher. The data were collected whi le varying eight etching variables. The relevance of electrode power, pressure, and gas flow rates is presented and has been found t o agree with observations reported in the literature. The observed behavior presented in this report serves as a tool to locate a nd optimize operating conditions to etch high aspect ratio structures. The performance of this deep reactive ion etcher allows the tai loring of silicon etching rates in excess of 4 mm/min with anisotropic profiles, nonuniformities of less than 4% across the wafer, and ARDE control with a depth variation of less than 1 mm for trenches of dissimilar width. Furthermore it is possible to prescribe the slope of etched trenches from positive to reentrant. © 1999 The Electrochemical Society. S0013-4651(98)01-009-X. All rights reserved.

Growth of a Single Freestanding Multiwall Carbon Nanotube on each Nanonickel Dot

Abstract: Patterned growth of freestanding carbon nanotube(s) on submicron nickel dot(s) on silicon has been achieved by plasma-enhanced-hot-filament-chemical-vapor deposition (PE-HF-CVD). A thin film nickel grid was fabricated on a silicon wafer by standard microlithographic techniques, and the PE-HF-CVD was done using acetylene (C2H2) gas as the carbon source and ammonia (NH3) as a catalyst and dilution gas. Well separated, single carbon nanotubes were observed to grow on the grid. The structures had rounded base diameters of approximately 150 nm, heights ranging from 0.1 to 5 μm, and sharp pointed tips. Transmission electron microscopy cross-sectional image clearly showed that the structures are indeed hollow nanotubes. The diameter and height depend on the nickel dot size and growth time, respectively. This nanotube growth process is compatible with silicon integrated circuit processing. Using this method, devices requiring freestanding vertical carbon nanotube(s) such as scanning probe microscopy, field emissi...

Plating apparatus and method

Abstract: An apparatus for plating a conductive film directly on a substrate with a barrier layer on top includes anode rod (1) placed in tube (109), and anode rings (2, and 3) placed between cylindrical walls (107, 105), (103, 101) respectively. Anodes (1, 2, 3) are powered by power supplies (13, 12 and 11), respectively. Electrolyte (34) is pumped by pump (33) to pass through filter (32) and reach inlets of liquid mass flow controllers (LMFCs) (21, 22, 23). Then LMFCs (21, 22, 23) deliver electrolyte at a set flow rate to sub-plating baths containing anodes (3, 2, 1), respectively. After flowing through the gap between wafer (31) and the top of the cylindrical walls (101, 103, 105, 107 and 109), electrolyte flows back to tank (36) through spaces between cylindrical walls (100, 101), (103, 105), (107, 109), respectively. A pressure leak valve (38) is placed between the outlet of pump (33) and electrolyte tank (36) to leak electrolyte back to tank (36) when LMFCs (21, 22, 23) are closed. A wafer (31) held by wafer chuck (29) is connected to power supplies (11, 12 and 13). A drive mechanism (30) is used to rotate wafer (31) around the z axis, and oscillate the wafer in the x, y, and z directions shown. Filter (32) filters particles larger than 0.1 or 0.2 νm in order to obtain a low particle added plating process.

Sequencing of the recipe steps for the optimal low-dielectric constant HDP-CVD Processing

Abstract: A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate This layer is much less likely to form a haze or bubbles in the layer, and is less likely to desorb water vapor during subsequent processing steps than other FSG layers An undoped silicon glass (USG) liner protects the substrate from corrosive attack The USG liner and FSG layers are deposited on a relatively hot wafer surface and can fill trenches on the substrate as narrow as 08 μm with an aspect ratio of up to 45:1

Field-effect passivation of the SiO2Si interface

Abstract: The field-effect passivation of the interface of thermal oxides on silicon is experimentally investigated by depositing corona charges on the oxide of solar cells and of lifetime test structures. The open circuit voltage of solar cells with interdigitated rear contacts can be increased by +12 mV or decreased by −34 mV, respectively, by depositing positive or negative corona charges on top of the front oxide. The resulting effective surface recombination velocity, Seff, is determined on carrier lifetime test structures for different injection levels and charge densities using microwave-detected photoconductance decay and a new expression for the Auger-limited bulk lifetime. Seff can be varied between 24 cm/s and 538 cm/s on a 1 Ω cm p-type wafer with a thermal oxide of 105 nm thickness. The measurements are compared with theoretical predictions of an analytical model for the calculation of the surface recombination. Measured values for the capture cross sections and interface trap densities are used for th...

Low temperature silicon wafer bond process with bulk material bond strength

Abstract: The present invention includes a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing a first article that has a semiconductor surface and a second article that has a semiconductor surface. The semiconductor surfaces are annealed with an energy source wherein energy is confined to the semiconductor surfaces. The annealed surfaces are bonded to each other.

The surface/bulk micromachining (SBM) process: a new method for fabricating released MEMS in single crystal silicon

Abstract: This paper presents the surface/bulk micromachining (SBM) process to allow fabricating released microelectromechanical systems using bulk silicon. The process starts with a [111]-oriented silicon wafer. The structural patterns are defined using the reactive ion etching technique used in surface micromachining. Then the patterns, as well as sidewalls, are passivated with an oxide film, and bare silicon is exposed at desired areas. The exposed bare silicon is further reactive ion etched, which defines sacrificial gap dimensions. The final release is accomplished by undercutting the exposed bulk silicon sidewalls in aqueous alkaline etchants. Because {111} planes are used as etch stops, very clean structural surfaces can be obtained. Using the SBM process, 5-, 10-, and 100-/spl mu/m-thick arbitrarily-shaped single crystal silicon structures, including comb-drive resonators, at 5-, 30-, and 100-/spl mu/m sacrificial gaps, respectively, are fabricated. An electrostatic actuation method using p-n junction isolation is also developed in this paper, and it is applied to actuate comb-drive resonators. The leakage current and junction capacitance of the reversed-biased p-n junction diodes are also found to be sufficiently small for sensor applications. The developed SBM process is a plausible alternative to the existing micromachining methods in fabricating microsensors and microactuators, with the advantage of using single crystal silicon.

Semiconductor wafer boat with reduced wafer contact area

Abstract: A boat for semiconductor wafers has reduced contact surface area with the wafer, thereby preventing distortion of the wafer during heating The boat has an upper member; a lower member, a plurality of wafers being loaded between the upper member and the lower member; and a plurality of support members vertically extended between and connecting the upper member to the lower member for supporting the wafers A plurality of slots are successively and horizontally formed in each of the support members, and the peripheral edge of the wafer is inserted therein, wherein a hemisphere-shaped protrusion is formed inside the slot, and the bottom surface of the wafer contacts and is supported by each hemisphere-shaped protrusion at a single contact point

Methods and apparatus for electropolishing metal interconnections on semiconductor devices

Abstract: An electropolishing apparatus for polishing a metal layer formed on a wafer (31) includes an electrolyte (34), a polishing receptacle (100), a wafer chuck (29), a fluid inlet (5, 7, 9), and at least one cathode (1, 2, 3). The wafer chuck (29) holds and positions the wafer (31) within the polishing receptacle (100). The electrolyte (34) is delivered through the fluid inlet (5, 7, 9) into the polishing receptacle (100). The cathode (1, 2, 3) then applies an electropolishing current to the electrolyte to electropolish the wafer (31). In accordance with one aspect of the present invention, discrete portions of the wafer (31) can be electropolished to enhance the uniformity of the electropolished wafer.

Recent advances in silicon etching for MEMS using the ASE™ process

Abstract: In the ongoing enhancement of MEMS applications, the STS Advanced Silicon Etch, ASE™, process satisfies the demanding requirements of the industry. Typically, highly anisotropic, high aspect ratios profiles with fine CD control are required. Selectivities to photoresist of 150:1 with Si etch rates of up to 7 μm/min are achievable. Applications range from shallow etched optical devices to through wafer membrane etches. This paper details some of the fundamental trends of the ASE™ process and goes on to discuss how the process has been enhanced to meet product specifications. Parameter ramping is a powerful technique used to achieve the often conflicting requirements of high etch rate with good profile/CD control. The results are presented in this paper.

Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method

Abstract: There is provided a method of fabricating an SOI wafer having high quality by hydrogen ion delamination method wherein a damage layer remaining on the surface of the SOI layer after delamination and surface roughness are removed maintaining thickness uniformity of the SOI layer. According to the present invention, there are provided a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after bonding heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; a method of fabricating an SOI wafer by hydrogen ion delamination method wherein an oxide film is formed on an SOI layer by heat treatment in an oxidizing atmosphere after delaminating heat treatment, then the oxide film is removed, and subsequently heat treatment in a reducing atmosphere is performed; and an SOI wafer fabricated by the methods.

Raman microspectroscopy study of processing-induced phase transformations and residual stress in silicon

Abstract: Raman spectroscopy was used for analysis of phase transformations and residual stress in machined silicon. Wear debris from dicing of silicon was scanned with a Raman spectrometer. Recorded spectra manifest the presence of amorphous Si, hexagonal phase (Si-IV), bc8 phase (Si-III) and pristine Si-I under residual stress. On surfaces of diced wafers as well as lapped silicon wafers, the r8 phase (Si-XII) was detected in addition to the above phases. The composition of phases in diced cross sections of silicon wafers differs dramatically between high and low speed cuts. The quantification of these phases was attempted by curve fitting each spectrum with corresponding peaks of each phase. Subsequently, relative intensity maps of specific phases were generated. Thus, Raman spectroscopy studies of machined surfaces demonstrated metallization of Si under a variety of machining conditions including lapping, grinding, scratching, dicing and slicing. All metastable phases of silicon disappear after etching and polishing of respective wafers. No evidence of phase transformations was found on a quartz-damaged silicon wafer surface. Residual stress having a characteristic distribution was observed in this case.

Semiconductor interconnect having laser machined contacts

Abstract: An interconnect for semiconductor components such as dice, wafers and chip scale packages is provided. The interconnect includes a substrate, and patterns of contacts formed on a face side of the substrate adapted to electrically engage external contacts (e.g., bond pads, solder bumps) on the components. The interconnect also includes insulated conductive members through the substrate, which provide direct electrical paths from the interconnect contacts to a backside of the substrate. The conductive members can be formed by laser machining openings in the substrate, and then filling the openings with a conductive material (e.g., metal, conductive polymer). The conductive members can also include pads with contact balls, configured for electrical interface with a test apparatus, such as test carrier or wafer handler. The interconnect can be used to construct test systems for testing semiconductor components, or to construct chip scale packages and multi chip modules.

Quasi-remote plasma processing method and apparatus

Abstract: In a plasma processing apparatus, a showerhead is provided that allows for selective ionization of one or more process gasses within the showerhead. The showerhead allows the gasses to react after they exit the showerhead. As a result, a greater volume of materials are. available for deposition on a wafer surface during a chemical vapor deposition process than would be available in a process that remotely generates plasma. In addition, less damage is done to the wafer that would be done in a process that generates plasma next to the wafer.

Electron field emission from silicon nanowires

Abstract: Silicon nanowires (SiNWs) were synthesized using laser ablation. A continuous SiNW film was prepared by grinding the pieces of sponge-like SiNWs to powder, then dispersing and sticking the powder onto a Si wafer. The field emission characteristics of the SiNW film were studied based on current–voltage measurements and the Fowler–Nordheim equation. The electron field emission increased with decreasing diameter of SiNWs. A hydrogen plasma treatment of the SiNW film aimed at reducing the oxide overlayer improved the emission uniformity of the film.

Fabrication ultra-thin bonded semiconductor layers

Abstract: The invention uses implantation, typically hydrogen implantation or implantation of hydrogen in combination with other elements, to a selected depth into a wafer with that contains one or more etch stops layers, treatment to split the wafer at this selected depth, and subsequent etching procedures to expose etch stop layer and ultra-thin material layer. A method for making an ultra-thin material layer bonded to a substrate, has the steps: (a) growing an etch stop layer on a first substrate; (b) growing an ultra-thin material layer on the etch stop layer; (c) implanting an implant gas to a selected depth into the first substrate; (d) bonding the ultra-thin material layer to a second substrate; (e) treating the first substrate to cause the first substrate to split at the selected depth; (f) etching remaining portion of first substrate to expose the etch stop layer, and (g) etching the etch stop layer to expose the ultra-thin material layer.

Vertical plasma enhanced process apparatus and method

Abstract: A plasma enhanced chemical vapor deposition (PECVD) system having an upper chamber for performing a plasma enhanced process, and a lower chamber having an access port for loading and unloading wafers to and from a wafer boat. The system includes apparatus for moving the wafer boat from the upper chamber to the lower chamber. The wafer boat includes susceptors for suspending wafers horizontally, spaced apart in a vertical stack. An RF plate is positioned in the boat above each wafer for generating an enhanced plasma. An RF connection is provided which allows RF energy to be transmitted to the RF plates while the wafer boat is rotated. Apparatus for automatic wafer loading and unloading is provided, including apparatus for lifting each wafer from its supporting susceptor and a robotic arm for unloading and loading the wafers.

Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer

Abstract: In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.

Gas distribution apparatus for semiconductor processing

Abstract: A baffle plate of a showerhead gas distribution system and method of using the baffle plate wherein the baffle plate is effective for reducing particle and/or metal contamination during processing of semiconductor substrates such as silicon wafers. The showerhead can be a showerhead electrode of a plasma processing chamber such as an etch reactor. The baffle plate comprises silicon on at least one surface thereof and is adapted to fit in a baffle chamber of the gas distribution system such that the silicon containing surface is adjacent to and faces the showerhead. The silicon containing baffle plate can consist entirely of silicon or silicon carbide of at least 99.999% purity. The silicon can be single crystal silicon or polycrystalline and the silicon carbide can be CVD silicon carbide, sintered silicon carbide, non-sintered silicon carbide or combination thereof. The non-sintered silicon carbide can be silicon carbide formed by reaction synthesis of silicon vapor with a carbon material such as graphite. Openings in the silicon containing baffle plate can be offset from openings in the showerhead to avoid a line-of-sight between plasma in the chamber and the openings in the silicon containing baffle plate.

Oxygen-free, dry plasma process for polymer removal

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the substrate, the conductive structure comprised of an oxygen-sensitive conductor; forming a layer of dielectric material over the conductive structure (step 306 of FIG. 1 ); forming a photoresist layer over the layer of the dielectric material (step 308 of FIG. 1 ); patterning the layer of the dielectric material (step 308 ); removing the photoresist layer after patterning the layer of the dielectric material (step 312 of FIG. 1 ); and subjecting the semiconductor wafer to a plasma which incorporates the combination of hydrogen or deuterium and a fluorine-containing mixture which is comprised of a gas selected from the group consisting of: CF 4 , C 2 F 6 , CHF 3 , CFH 3 and other fluorine-containing hydrocarbon (step 313 of FIG. 1 ).

Wafer transfer mechanism

Abstract: A transfer mechanism is provided for placing a wafer at a prescribed position on an arm without any additional step. The transfer mechanism for transferring a workpiece into and from a storage section comprises an arm member for holding a workpiece having a projection which can be contacted with an edge of the workpiece at the tip end portion thereof, a movement mechanism for reciprocating the arm member between a retracted and an extended positions while holding the workpiece thereon to transfer the workpiece to and from the storage section, and a positioning member which is positioned in the vicinity of the arm member and can be contacted with the edge of the workpiece for positioning the held workpiece in a prescribed position on the arm member. When the arm member is moved to the retracted position by the movement mechanism, the positioning member comes into contact with the edge of the workpiece held on the arm member to block only the movement of workpiece, thereby placing it in a prescribed location on the arm member.

The effect of surface roughness on direct wafer bonding

Abstract: A theory is presented which describes the initial direct wafer bonding process. The effect of surface microroughness on the bondability is studied on the basis of the theory of contact and adhesion of elastic solids. An effective bonding energy, the maximum of which is the specific surface energy of adhesion, is proposed to describe the real binding energy of the bonding interface, including the influence of the wafer surface microroughness. Both the effective bonding energy and the real area of contact between rough surfaces depend on a dimensionless surface adhesion parameter, theta. Using the adhesion parameter as a measure, three kinds of wafer contact interfaces can be identified with respect to their bondability; viz. the nonbonding regime (theta > 12), the bonding regime (theta < 1), and the adherence regime (1 < theta < 12). Experimental data are in reasonable agreement with this theory

Thermal CVD process for depositing a low dielectric constant carbon-doped silicon oxide film

Abstract: A method for providing a dielectric film having a low dielectric constant. The deposited film is particularly useful as an intermetal or premetal dielectric layer in an integrated circuit. The low dielectric constant film is a carbon-doped silicon oxide layer deposited from a thermal, as opposed to plasma, CVD process. The layer is deposited from a process gas of ozone and an organosilane precursor having at least one silicon-carbon (Si—C) bond. During the deposition process the wafer is heated to a temperature less than 250° C. and preferably to a temperature between 100-200° C. Enhancements to the process include adding Boron and/or Phosphorus dopants, two step deposition, and capping the post cured layer.

GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor

Abstract: A GaN crystal film having a mask patterned in a stripe for forming multiple growing areas on a sapphire substrate and coalesced GaN crystals covering the mask dividing the areas, grown from the neighboring growing areas, comprising defects where multiple dislocations along with the stripe are substantially aligned with the normal line of the substrate, in the crystal areas over the mask, and dislocations propagating in substantially parallel with the substrate surface while, in the vicinity of the areas where the crystals are coalesced over the mask, propagating substantially in the normal line of the substrate surface, and a manufacturing process therefor. According to this invention, there can be provided a GaN crystal film in which strain, defects and dislocations are reduced and which tends not to generate cracks.

Distributed control system architecture and method for a material transport system

Abstract: There is provided a chemical vapor deposition apparatus for depositing substantially uniform films or layers onto a substrate or wafer. The apparatus includes a chamber with an injector assembly including spaced linear injectors and a chemical vapor delivery system for delivering chemicals to said injectors to form spaced adjacent deposition regions. Translation means reciprocally move said substrate or wafer a predetermiend distance in a direction perpendicular to the long axis of the linear injectors while maintaing the substrate surface parallel and adjacent to the chemical delivery surface of the linear injector assembly whereby the deposition regions of adjacent injectors merge to form a film or layer of substantially uniform thickness.

System for improving energy purity and implant consistency, and for minimizing charge accumulation of an implanted substrate

Abstract: A plasma immersion ion implantation method and system is provided for maintaining uniformity in implant energy distribution and for minimizing charge accumulation of an implanted substrate such as a wafer. A voltage modulator (27) applies a pulsed voltage signal (−Vp) to a platen (14) in a process chamber (17) containing a plasma, so that ions in the plasma are attracted by and implanted into a wafer residing on the platen. The voltage modulator (27) comprises: (i) a first switch (50) disposed between a power supply (48) and the platen for momentarily establishing a connection therebetween and supplying the pulsed voltage signal to the platen; (ii) a second switch (54) disposed between the platen (14) and ground for at least momentarily closing to discharge residual voltage (−Vr) from the platen after the first switch (50) opens and the connection between the power supply and the platen is broken; and (iii) a controller (56) for controlling sequential operation of the switches (50, 54). By closing second switch (54) and grounding the platen, (a) only ions within a certain energy level range are implanted into the wafer, improving the implant energy distribution and (b) wafer charging due to implantation of positive ions is neutralized by allowing electrons in the plasma to flow toward the wafer between implant pulses. Upon opening, second switch (54) permits the platen to float to achieve the floating potential of the plasma thus minimizing voltage stresses on devices in the wafer. Alternatively, the platen may be positively biased to the plasma floating potential.

Method of and apparatus for restoring a support surface in a semiconductor wafer processing system

Abstract: Method and apparatus for restoring a support surface of a substrate support to a pre-process condition. The method comprises the steps of providing a surrogate substrate on the degraded support surface, providing the surrogate substrate with a ground connection and establishing an electric field between the support surface and the surrogate substrate to remove accumulated charges in the support surface. The apparatus comprises a process chamber having a surrogate substrate on a the support surface and connected to ground. The surrogate substrate is a semiconductor wafer or a plate or sheet of metallic material. The ground connection is established by striking a plasma that contacts the surrogate substrate and an electrical ground reference. The electric field established between the support surface and the surrogate substrate "pushes" any accumulated charges out of the support surface. Removal of the accumulated charges improves and extends the chucking ability of the support surface. The subject method also maintains the integrity of the support surface material as it is not attacked by highly energized and/or reactive species in a plasma.