There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

Introduction to Electromagnetic Compatibility

Antenna Theory And Design

Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

Widespread use of the Web 2.0 Internet applications such as video streaming and social networking are continuously demanding higher bandwidth network equipment. Electrical designers increasingly face more and more challenges to deliver higher speed products within short development cycle due to design complexity and new multi-GHz signal integrity problems. This paper presents a modeling and simulation methodology through chip/package/PCB (printed circuit board) co-design and co-optimization to enable a terabit per second network switch linecard design. Channel design techniques such as BGA (Ball Grid Array) pin backdrill, via tuning, and low loss interconnects are outlined. Full wave 3D modeling techniques with optimal model segmentation, model cascading and model optimization are discussed. At the end, correlation between lab measurement and simulation in both frequency and time domains are investigated.

Enabling terabit per second switch linecard design through chip/package/PCB co-design

The assumption of transverse electromagnetic (TEM) field distribution on via holes is checked by a two-dimensional (2D) finite difference method (FDM). It is found that for a via without pad, TEM mode assumption is a quite good approximation. However, for a via with a pad, i.e. the via pad radius is different from the via barrel radius, the field distribution on the via hole begins to deviate from the TEM mode. This indicates previous analytical formula for a via with pad may need to be modified at very high frequencies due to its usage of TEM field assumption on via holes. The results obtained by 2D FDM have been verified by a three-dimensional commercial electrostatic solver.

Studies of TEM mode assumption on via holes in via modelings

Printed circuit board (PCB) design is getting critical as data rate approaching 25 Gbps (Gigabit per second) and beyond in networking systems. Channel loss, noise coupling and discontinuities are limiting the performance of high-speed channels. Equalization techniques including linear, feed forward and decision feedback are widely used in high-speed SerDes channels to compensate the channel losses. But these are still not sufficient for some extra long channels, and low loss PCB dielectric materials have to be used finally. The consequence is the cost of the networking system soaring significantly. In this paper, a hybrid stack-up is proposed for PCBs used in networking systems. Electrical performance of the hybrid stack-up is investigated in both frequency-domain and time-domain, and a positive conclusion for the hybrid stack-up is reached based on its cost and electrical performances.

A hybrid stack-up of printed circuit board for high-speed networking systems

A printed circuit board has one or more layers on which electrically conductive traces reside. The printed circuit board also includes a thru-hole via formed in one or more of the layers. The thru-hole via includes at least two electrically conductive portions that are electrically isolated from each other, where the electrically conductive portions connect electrically to separate conductive traces.

Passing multiple conductive traces through a thru-hole via in a pcb

A well-designed power delivery network (PDN) demands a set of efficient and effective modeling and optimization methodology for the Chip-Package-PCB System. This paper work provided and validated the hybrid target impedance for the PDN impedance optimization in frequency domain and the physics-based equivalent circuit model with small signal model for voltage response validation in time domain. The hybrid target impedance defined with current profile-based discrete and continuous target impedance. Two key impedance points in discrete were identified for on-chip worst case switching scenario and voltage regulator module switching ripple, more points can be added if specific core power switching scenario identified. The continuous impedance points are from the conventional target impedance by voltage ripple to dynamic current change. This hybrid method provides a more effective and convergent way to perform system level decoupling capacitors optimization in frequency domain and to meet voltage specification in time domain, also to avoid overdesigning for cost saving.

Jun Fan

Papers

Enabling terabit per second switch linecard design through chip/package/PCB co-design

Studies of TEM mode assumption on via holes in via modelings

A hybrid stack-up of printed circuit board for high-speed networking systems

Passing multiple conductive traces through a thru-hole via in a pcb

Power Delivery Network Optimization Approach using an Innovative Hybrid Target Impedance