J
Jun Fan
Researcher at Missouri University of Science and Technology
Publications - 505
Citations - 7033
Jun Fan is an academic researcher from Missouri University of Science and Technology. The author has contributed to research in topics: Printed circuit board & Equivalent circuit. The author has an hindex of 36, co-authored 482 publications receiving 5641 citations. Previous affiliations of Jun Fan include Ulsan National Institute of Science and Technology & University of Missouri.
Papers
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Proceedings ArticleDOI
A Comprehensive and Practical Way to Look at Crosstalk for Transmission Lines with Mismatched Terminals
TL;DR: This paper re-define the far-end crosstalk (FEXT) as a combination of several components generated by different coupling and reflection mechanisms, and a new set of crosStalk estimation formulas is developed to calculate the contribution of each component.
Proceedings ArticleDOI
Design methodology for PDN synthesis on multilayer PCBs
Bruce Archambeault,Matteo Cocchini,G. Selli,Jun Fan,James L. Knighten,Samuel Connor,Antonio Orlandi,James L. Drewniak +7 more
TL;DR: In this paper, a step-by-step process to design the decoupling strategy for the charge supply is described, where the distance from the decouple capacitors to the ground plane, the number of decoupled capacitors, and the inductance associated with the connection of the decouppling capacitor to the power and ground reference planes will all influence how much charge is delivered.
Proceedings ArticleDOI
Analysis of via impedance variations with a Polynomial Chaos method
TL;DR: A systematic framework for the optimization and analysis of the equivalent characteristic impedance of practical via structures using Polynomial Chaos method, which naturally leads to a rigorous methodology for EM design/control in the presence of multiple sources of uncertainty.
Journal ArticleDOI
Statistical Eye Diagram Analysis Based on Double-Edge Responses for Coding Buses
TL;DR: A new statistical method is proposed to estimate the worst-case eye diagrams and bit-error-rate (BER) eye diagrams for coding buses and eliminates the error due to the invalid assumption and provides more accurate results for designers.
Journal ArticleDOI
Capacitance-Enhanced Through-Silicon Via for Power Distribution Networks in 3D ICs
TL;DR: In this paper, the authors proposed a through-silicon via (TSV) structure with enhanced capacitance for the power distribution network in 3D ICs, where an n+ contact on the top surface surrounding the oxide silicon interface of the power TSV is used, instead of a p-substrate.