T
Tetsu Tanaka
Researcher at Tohoku University
Publications - 423
Citations - 11239
Tetsu Tanaka is an academic researcher from Tohoku University. The author has contributed to research in topics: Wafer & Chip. The author has an hindex of 38, co-authored 406 publications receiving 10375 citations. Previous affiliations of Tetsu Tanaka include NTT DoCoMo & Tokyo Medical and Dental University.
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Proceedings ArticleDOI
Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers
K. W. Lee,C. Nagai,Ai Nakamura,H. Aizawa,Jichoel Bea,Mitsumasa Koyanagi,H. Hashiguchi,Takafumi Fukushima,Tetsu Tanaka +8 more
TL;DR: High yield reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology is proposed for ultra-high density 2.5D/3D integration applications to avoid the issues of current standard CoW bonding technology.
Proceedings ArticleDOI
A resilient 3-D stacked multicore processor fabricated using die-level 3-D integration and backside TSV technologies
Kang-Wook Lee,Hideki Hashimoto,M. Onishi,Y. Sato,M. Murugesan,Jichoel Bea,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +8 more
TL;DR: A 3D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed in this article, which is implemented using die-level 3D integration and backside TSV technologies.
Journal ArticleDOI
Multilevel Charge Storage in a Multiple Alloy Nanodot Memory
TL;DR: A multilevel charge storage in a multiple FePt alloy nanodot memory is investigated for the first time in this article, where it is demonstrated that the memory structure with multiple FEPt nanodots layers effectively realizes a multi-level state by the adjustment of gate voltage.
Proceedings ArticleDOI
Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration
TL;DR: The bonding characteristics of the novel detachable bonding process was estimated by evaluating the shear strength and the dissolution time of adhesive material varying the ratio of hydrophobic area to the hydrophilic area using 5 mm2 size chip.
Proceedings ArticleDOI
Minimized hysteresis and low parasitic capacitance TSV with PBO (polybenzoxazole) liner to achieve ultra-high-speed data transmission
TL;DR: In this paper, the authors proposed the deployment of polybenzoxazole (PBO) as the polymer-liner material of TSV for minimizing the capacitance modulation, and a metal-insulator-semiconductor (MOS) capacitor with blind TSV structure was fabricated with PBO and PI liners.