T
Tetsu Tanaka
Researcher at Tohoku University
Publications - 423
Citations - 11239
Tetsu Tanaka is an academic researcher from Tohoku University. The author has contributed to research in topics: Wafer & Chip. The author has an hindex of 38, co-authored 406 publications receiving 10375 citations. Previous affiliations of Tetsu Tanaka include NTT DoCoMo & Tokyo Medical and Dental University.
Papers
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Journal ArticleDOI
Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks
TL;DR: This study generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure that enables the implementation of low-operation-voltage SNNs.
Proceedings ArticleDOI
Development of Si Double-sided Microelectrode for Platform of Brain Signal Processing System
Risato Kobayashi,S. Kanno,Takafumi Fukushima,Kazuhiro Sakamoto,Norihiro Katayama,Hajime Mushiake,Tetsu Tanaka,Mitsumasa Koyanagi +7 more
TL;DR: In this article, the authors proposed a method to solve the problem of bioengineering and robotics at Tohoku University by using a bio-inspired approach based on the Aza-Aoba algorithm.
Proceedings ArticleDOI
New Reconfigurable Memory Architecture for Parallel Image Processing LSI with Three-Dimensional Structure
Shigeo Kodama,Daijiro Amano,Takeaki Sugimura,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +5 more
TL;DR: In this paper, a reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed, which can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data.
Proceedings ArticleDOI
Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion
Kousei Kumahara,Rui Liang,Sungho Lee,Yuki Miwa,Mariappan Murugesan,Hisashi Kino,Takafumi Fukushima,Tetsu Tanaka +7 more
TL;DR: In this article, the authors verify the effectiveness of room-temperature CVD named OER (Ozone-Ethylene Radical generation)-TEOS-CVD® to deposit a TSV liner SiO 2 layer.
Proceedings Article
3D LSI technology and reliability issues
TL;DR: In this article, the authors describe mechanical stresses caused by Cu TSVs and CuSn microbumps and design guideline to minimize stress effects on 3D LSIs, which is the most promising technology to enhance LSI performance beyond scaling theory.