Proceedings ArticleDOI
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
Janakiraman Viraraghavan,Derek H. Leu,Balaji Jayaraman,Alberto Cestero,Robert E. Kilker,Ming Yin,John Golz,Rajesh R. Tummuru,Ramesh Raghavan,Dan Moy,Thejas Kempanna,Faraz Khan,Toshiaki Kirihata,Subramanian S. Iyer +13 more
- pp 1-2
TLDR
An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity.Abstract:
An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (∼30%) to satisfy 10 year retention at 105° C.read more
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An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT)
Yuan Du,Li Du,Xuefeng Gu,Jieqiong Du,X. Shawn Wang,Boyu Hu,Jiang Ming-Zhe,Xiaoliang Chen,Su Jun-Jie,Subramanian S. Iyer,Mau-Chung Frank Chang +10 more
TL;DR: In this paper, an analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed, which is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces.
Proceedings ArticleDOI
Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology
TL;DR: In this paper , the charge-trap transistor (CTT) has been proposed to overcome the low on/off ratio, large IR drop, limited retention capability, and additional process complexity for embedding in commercial CMOS logic.