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A Study of Tapered 3-D TSVs for Power and Thermal
Integrity
Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi
Dilillo, Arnaud Virazel
To cite this version:
Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, et al.. A Study
of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, IEEE, 2013, 21 (2), pp.306-319. �10.1109/TVLSI.2012.2187081�. �lirmm-
00806776�
306 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEM S, VOL. 21, NO. 2, FEBRUARY 2013
A Study of Tapered 3-D TSVs for Power
and Thermal Inte gr i t y
Aida Todri, Memb e r, IEEE, Sandip Kundu, Fello w, IEEE, Patrick Girard, Senior Member, IEEE,
Alberto Bosio, Member, IEEE, Luigi Dilillo, Member, IEEE, and Arnaud Vir az e l, Member, IE EE
Abstract—3-D integration p resent s a path to higher perfor-
mance, greater density, increased f unctionality and heterogeneous
technology imp lementation. Howeve r, 3-D integration introduces
many challenges for power and thermal integrity due to large
switching currents, longer power delivery paths, and increased
parasitics compared to 2-D integration . In this wor k, we provide
an in-depth study of p ower and thermal issues while incorporating
the physical design characterist ics unique to 3-D integration.
We provide a qual itative perspective of the power and thermal
dissipation issues in 3-D and study the impac t of Through Silicon
Vias (TSVs) size for their mitigation . We investigate and discuss
the design implicati ons of power and thermal issues in the pres-
ence of decoupling capacitors, TSV/o n-die/package parasitics,
various resonance effects and power gating. Our study is based on
a ten-tier system utili zing existing 3-D technology specifications.
Based on detailed power distribution and heat dissipat io n models,
we present a comprehensive an alysis of TSV tapering for allevi-
ating power and thermal integrity issues in 3-D ICs.
Index Terms— 3-D integration, power and the rmal ana ly sis,
power delivery.
I. INTRODUCTION
T
HE RECENT advancements in semiconductor processing
technologies have enabled three dimensional circuit de-
sign and implementation o f heterog eneous systems in the
same platform, i.e., Flash, DRAM, SRAM p laced atop logic
device s and microprocessor cores [1]. 3-D vertical integration
results in shorter interconnect len gths, greater device density
and enhanced performance. However, the densely packe d
vertica l tiers introduce significant power and thermal integrity
challenges compared to 2-D integration.
Power delivery i n 3-D systems draws much larger current
from package and power/ground net works than in conventional
2-D systems due to multiple tiers [2]. The large current de-
mand leads to significant voltage droop (accumulated
drop,
Manuscript received September 06, 2011; revised January 11, 2012; accepted
Janua ry 16, 2012. Dat e of publication March 22, 2012; date of current version
January 17, 2013.
A. Todri, P. Girard, A. Bosi o, L. Dilillo, and A. Virazel are with the
Laboratoire d’Informatique de Roboti que et de Microélectronique de M ont-
pellier (LIRMM, CNRS UMR 5506), Montpellier 34095, France (e-mail:
todri@l irmm.fr; girard@lirmm.fr; bosio@lirmm.fr; dilillo@lirmm.fr; vi-
razel@lirmm.fr)
S. Kundu is with the Departme nt of Electrical and Computer Engineering
Department, University of Massachusetts, Amherst, MA 01003-9284 USA
(e-mail: kundu@ecs.uma ss.edu).
Color versions of one or more of the figures in this paper are available online
at http: //ieeexplore.ieee.org.
Dig
ital Object Identifier 10.1109/TVLSI.2012.2187081
Fig. 1. Illustration of multi-tier system with through silicon vias. Voltage droop
and temperature increase in opposite direction.
and effec
ts) due to the parasitics of power
and ground networks. Fu
rthermore, the surge of current can lea d
to considerable
e
ffects due to on-chip and package induc-
tances.
Due to the increased p
ower density a nd greater thermal r e-
sistanc e to h eat sin
k, thermal integrity is a crucial challenge
for reliable 3-D in
tegrat ion. High temperatures can degrade the
reliab ility and pe
rformance of interconnects and devices [3].
Power/ground net
work resistivity is a function of t emperature,
thus at nod es wit
h high tempe rature, voltage droop values be-
come even wors
e. Furthermore, the large amount of current on
power and grou
nd networks flowing for significant amount of
time can ulti
mately elevate the temperature and cause Joule
heating and
electromigration [4]. Thus, voltage droop and tem-
perature ar
e interdependent and should be considered simulta-
neousl y du
ring analysis. Fig. 1 shows an illustration of a 3-D
system an
d de picts the opposing direction of voltage droop and
tempera
ture increase. Voltage d roop tends to increase for tiers
further
away from package controlled-colla pse chip-connection
(C4) bu
mps and close to heat sink while temperature increases
for ti
ers further awa y from heat sink and near to package pins.
While 3
-D technology is still m aturing, the following ques -
tions
must be addressed for an accurate understanding of the
crit
icality of power and thermal in tegrity issues in 3-D systems.
• How si
gnificant is the volta ge droop im pact of an actively
swit
ching tier on n eighboring tiers? Do decoupling capac-
itor
s of neighboring tiers provi de an y mitigation?
• How c
ritical are power supply noise and heat dissipation
on a m
ulti-tier syst em?
• What
is the impa ct of powe r gating an entire tier?
• What i
s the impact of resonant frequency of a power de-
live
ry network (PDN) i n 3-D sys tems?
• Does T
SV sizing play a role?
• Are ta
pered TSVs more effective in mitigati ng power and
therm
al integrity problems, and if so, what are the des ign
impl
ications?
1063-8210/$31.00 © 2012 IEEE
TODRI et al.: STUDY OF TAP ERED 3-D TSVS FOR POWER AND THERMAL INTEGR ITY 307
To answer these questions, it requires accurate modeling and
analys is to account for all the physical e ffects unique to 3-D in-
tegration. Our t arget platform is a ten-tier 3-D system consisting
of tiers that dissipate identical power, unless a tier is power gated
or s ubject to dynamic frequency scaling. Further, we assume
that the number of power/ground TSVs connecting any two ad-
jacent tiers is the same. TSVs may only vary in their cross-sec-
tional area. We investigate optimal tapering of TSVs under the
above constraints. We a lso assume a 3-D power delivery net-
work, wher e e ach tier has its own de livery networ k connected
through power/ground TSVs.
This study presents a comprehensive power an d thermal
co-analysis for 3-D integrated systems.
models ar e used
for TSVs and pow er/ground networks. Models are flexible to
represent TSVs of di fferent dimensions and extracted for high
freque ncies in order to capture the skin effect and substrate
coupling of TSVs as in [5]–[8]. Po wer and thermal analysis is
based on the well-known electrical-thermal duality principle.
Tapering of power/ground TSVs is investigated as means to
ease power and ther mal integrity issues in 3-D integration.
There ar e a few wo rks in the literature that aim at per-
forming both power and ther mal analysis for 3-D systems.
An electric al-thermal co-analysis method was proposed in [9],
howeve r, important physical l evel details were not co nsidered,
i.e., heat transfer among tie rs and TSVs skin effect. In [10] and
[11], a via stapling method for 3-D systems was proposed based
on power and ther mal integrity. In contrast to previous works,
we aim to pr ovide a comprehensive power-thermal co-analysis
to fully understan d the criti cality of pow er and thermal issues in
3-D systems. Furthermore, we investigate the impa ct of tapered
TSVs on power and thermal integrity.
The rest of this paper is organized as follows. Models
for TSVs, C4 and power/ground networks are present ed in
Section II. Our power-therma l co-analysis methodology is
presen ted in Section III. In Section IV, we pre sent several
case studies f or investigating 3-D power and thermal issues.
Section V discusses the impact of tapered TSVs. Section VI
presents de sign implications of using tapered TSVs. We con-
clude this paper i n Sectio n VII.
II. M
ODELS
We make use of 3-D technology specifications that are avail-
able from open literature to study power and thermal integrity
issues. Table I sum marizes the technology data that ar e refer-
enced t hroughout this secti on and so me are obtained from [12].
This section provides detailed descriptions of the models used
in our analysis.
To quantify the impact of TSVs on multi-tier systems, we uti-
lize detailed analytical models including
parasitics
from the package , on-ch ip power/ ground global distribution net-
works, TSVs, a nd underlying switching circ uits. Current is de-
livere d from the package pins t hrough C4 arrays, and then dis-
tribute d over the power network and TSVs through e ach tier
where switching circuits draw the current. Fig. 1 provides an il-
lustration of th e multi-tier systems considered in this work. It
is important to note that m odels discussed in this work are not
specifi c to any 3-D prototype.
TABLE I
T
ECHNOLOGY SPE CIFICATIONS
Fig. 2. Current provided by C4 bump with respect to its pitch [14].
A. C4 Model
C4 bumps are a technology standard for allowing high
wiring density and high si gnal bandwidth between the chi p and
packag e. Packaging industry is recently moving toward bump
arrays for high-density connections with bumps smal l er tha n
the standard
m diameter on m pitch [13]. Compared
to wire-bonding, flip-chip packaging with C4 b umps provi de a
significant improvement in po wer and g round network distri-
bution.
Detailed chara cterization of C4 bumps is performed by [14]
and Fig. 2 sh ows a plot of the C4 current with respect to C4
pitch for va ri ous power densit i es. In our analysis, we em ploy
standard si ze C4 wi th
m diameter on m pitch wit h
power density of 200 W/cm2. The current provided from each
C4 is 200 mA. The pa rasitics of C4 bump are
m and 60
pH. In this work, we consider a n array of C4s bumps and half
of them su pply power and ground, respectively.
For our analysis, we cons i der a portio n of the power and
ground network distribution which incl udes an array of C4s with
several power and grou nd C4 bumps. Chip footprint can be di-
vided into cells which a re identical square regions bet ween pair
308 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEM S, VOL. 21, NO. 2, FEBRUARY 2013
Fig. 3. Illustration of the powe r network area and 16 C4 power and ground
bumps that are considered in this analysis. Cell dimensions are
m by
m. Large cell dimensio ns are m by m.
Fig. 4. (a) Photograph of CU TSV [17]. (b) Electrical model of a TS V.
of adjacent power and g round pads as shown in Fig. 3. In litera-
ture, a small area of power grid such as the cell shown in Fig. 3
which is among two power and ground C4s is often used for
power analysis where d ue to symmetry it is assumed that no cur-
rent passe s in the normal direction to the cell border[15]. In this
work , we utilize a larger power network area
m m
and include several power/gro und C4s. This allows us to in-
vestigate the impact of seve ral power/ground pins for current
supply and represent more realistically the boundary conditions
between ce lls.
B. TSV Model
TSVs enable vertical integration and hav e a significant im-
pact on the power and thermal integrity of the system, as they in-
troduc e additional parasitics between each tier. TSVs [16], [18]
form a cylindrical metal-oxide-semiconductor (MOS) capacitor
with semiconductor substrate acting as the bulk and TSV metal
acting as a gate. TSVs al low voltage/s ignal distribution among
the tiers; how ever, they also behave as a medium for power
supply noise propagation from one tier to the ne xt. Similarly,
TSVs allow heat dissipation in vertical direction which is highly
dependent on the TSV geometry and cir cuit switching activity
on its surrounding. In this work, we consider copper filled TSV
as shown in Fig. 4(a).
Fig. 5. TSV distribution.
To determine the impac t of T SVs o n power and thermal in-
tegrity for multi-tier syste ms, we apply analytical models to ex-
press the resistance, indu ctance and cap acitance parasitics of the
TSV wi th respect to its physical dimensions. Th e values of the
parasitic
, , and are de rived as a function of
physical para meters, material chara cteristics and technology pa-
ramete rs [8]. Fig. 4(b) shows the electrical model o f a TSV.
The resistance of the TSV with respect to its radius,
and
length
is as
(1)
where
is the resistivity of the conducting material. Authors
in [17] perf ormed TSV charac terization with v arying frequen-
cies from 0 to 20 GHz. TSV resistance increas es with frequency
from 120 to
m due to skin effects [17]. In our analysis, we
perform a study with var ious swi tching frequencies to acc ount
for skin effect and represent various workloa ds.
TSV inductance is also derived through partial self-induc-
tance and mutual inductance. Partial self-inductance depends on
the diameter and length of TSV and is expressed as
(2)
where
is the permeability of free sp ace given b y
H/m. Additionally, mutual inductance between
TSVs has an impact on the overall inductance parasitic of a
TSV. Fig. 5 shows the TSV distribution assumed in this work.
Depending on the lo cation and spacing between th e neigh-
boring TSVs, mutual inductance can have an additi ve effect
when the current flow is in the same direction and a d iminutive
effect when cu rrent flows on opposit e direction, i.e., between a
power and ground TSV. Mutual inductance between two TSVs
can be derive d as
(3)
where
is the spacing between two TSVs. Spacing bet ween
two TSVs varies dep ending on their l ocation. For example, in
our study, m utual coupling between two neighbor TSVs in either
vertical or horizontal d irection hav e a space
m, while
TODRI et al.: STUDY OF TAP ERED 3-D TSVS FOR POWER AND THERMAL INTEGR ITY 309
two TSVs mutually couple d in diagonal direction have a space
of m as shown in Fig. 5. Thus, the inductance
for an y TSV i s computed taking into account the partia l self-
inductance and mutual inductances as
(4)
where
is the inductance for a po wer TSV and is
the inductance for ground TSV. Co efficient is the ratio of cur-
rents flowing through the TSV under investigation and its neigh -
borin g TSV as th e current flow on each TSV can differ based on
the switc hing activity of the underlying circuits. Furthermore,
the number of neighboring TSVs varies based on the location
of the TSV under investigation. F or example, a TSV located
on the boundary of the T SV array has fewer neighboring TSVs
than a TSV located in the center of the TSV array; hence their
mutu al inductance wou ld vary. Additionally, mutual in ductance
varies with respect to the distance between TSVs, as the space
betwee n two TSV increases, their coupling decreases as well.
Fig. 5 illustrates TS V array and inductance coupling betw een
neighboring T SVs and their effect ( i.e., additive or subtrac tive)
based on the direction of the current flow.
TSV capacitance can be derived by solvi ng Poisson’s equa-
tions for MOS capacitor structure in cylindri cal coordinate
system due to TSV shape [18]. It is sufficient to solve 1-D
Poisson’s equation along radial direction to obtain the capaci -
tance [8]. Equation (5) describes TSV capacit ance as a function
of oxide and depletion capacitan ce as
where
(5)
where
, are permittivity of oxide and silicon, respec tively.
As s hown in (5),
is directly proportional to the length
of TSV and inversely proportional to the dielectric thickness
of TSV. With increasing frequency up to 20 GHz, for
m
diameter TSV, its capacitance drops off from 3 0 to 5 fF [17].
In this work, we util ize parasitic values obtained up to 10 GHz
frequen cy and t heir values are list ed in Table II for d i fferent TSV
geometries.
C. Powe r and Ground Distribution Network
In 2-D high-performance designs, power d i stribution net-
works are commonly structured as a multi layered mesh grid
[19]. In such a grid, power tracks of each met al laye r span the
entire die and vias are inserted on intersections between them.
Power i s distributed over many metal tracks creating local
TABLE II
P
ARASITIC VALUE S OF A TSV
Fig. 6. Four tier 3-D system wi th TSVs and C4 bumps on top.
and global power grids. In 3-D multi-tier systems, power and
ground networks for each tier can be represented as a 2-D mesh
grid. Additionally, in 3-D systems, power d istribution networks
deliver power and ground voltages from pads t o all tiers passing
through the TSVs. TSV can be inserted BEOL (“via last”) or
FEOL (“via first”) [20]. In this analysis a “via last” appro ach is
assum ed which indicates that a TSV is connected to the global
power grid of one tier and to the local power grid of the next
tier. Fig. 6 illustrates this concept. The physical and an alytical
models described in this work can be applied to TSVs of any
size and approach, i.e., represe nting “via first” approach would
differ the power network size and granularity (local or g lobal
network ) that is connected through the TSV from one tier to an-
other. In the following subsections, both electri cal and ther mal
models of powe r/ground distribution networks are described.
D. Electrical Model
Our an alysis considers dynamics power analysis by including
parasitics of the 3-D multi-tier system. The extracted par-
asitics represent the packa ge (C4 bumps), pow er/ground net-
works, switching cir cuits, decoupling capacitance (in tentionally
insert ed capacitance and/or equivalent capa citance fro m non-
switching circuit s), and TSVs. We assume a uniform distribu-
tion of power/ground TSVs among all tiers. Power and ground
grids for each tier vary in gr anularity and track dimensions de-
pending o n TSV connection which represent either a local or
global grid for the given grid area. Power an alysis is applied
on the large cell area as described in the previous S ection II-A.
Package p arasitics are modeled by r esistance,
and induc-
tance,
. Pow er and ground networks are modeled by re-
sistan ce,
and capacitance, . Switching circuits on
each tier are modeled as time-varying current sour ces to rep-
resent the electrical charac teristics of the underlying hardware
in terms of: 1 ) switc hing frequency; 2) peak current ; 3) lea kage
