Journal ArticleDOI
Development of a simulator for analyzing some performance parameters of nanoscale strained silicon MOSFET-based CMOS inverters
TLDR
A simulator has been developed for evaluating the voltage transfer characteristics (VTC) and analyzing some performance parameters of such devices-based CMOS inverters and can be applied to any novel device structure and complex digital logics.About:
This article is published in Microelectronics Journal.The article was published on 2016-09-01. It has received 8 citations till now. The article focuses on the topics: Transconductance & MOSFET.read more
Citations
More filters
Numerical Methods For Partial Differential Equations
TL;DR: Numerical methods for partial differential equations is available in the digital library an online access to it is set as public so you can download it instantly and is universally compatible with any devices to read.
Journal ArticleDOI
Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications
TL;DR: In this paper, an analytical model of the threshold voltage and drain current for gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field effect transistors (MOSFETs) was proposed.
A strained Si-channel NMOSFET with low field mobility enhancement of about 140% using a SiGe virtual substrate
TL;DR: In this paper, a fully standard CMOS integrated strained Si-channel NMOSFET has been demonstrated, where the thickness of graded SiGe, modifying the channel doping concentration, changing the Ge fraction of the relaxed SiGe layer and forming a p-well by multiple implantation technology was fabricated.
Journal ArticleDOI
Pathways of NO adsorption on Si(100)2×1 by van der Waals corrected DFT
TL;DR: In this article, the authors investigated the NO adsorption on the Si(100) surface, including van der Waals forces (vdW), and found stable molecular and dissociative configurations.
Book ChapterDOI
On-Chip Carbon Nanotube Interconnects: Adaptation to Multi-gate Transistors
Subindu Kumar,Tarun Kumar Sharma +1 more
TL;DR: In this paper, the effects of using MGT-based driver circuits using gate-all-around (GAA) devices have been discussed and methods for improving interconnect delay using GAA devices in presence of device variability have also been presented.
References
More filters
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
Short-channel effect in fully depleted SOI MOSFETs
TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Journal ArticleDOI
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,Mohsen Alavi,M. Buehler,R. Chau,S. Cea,Tahir Ghani,G. Glass,T. Hoffman,Chia-Hong Jan,C. Kenyon,Jason Klaus,K. Kuhn,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,B. Obradovic,Ramune Nagisetty,P. Nguyen,Swaminathan Sivakumar,R. Shaheed,Lucian Shifren,B. Tufts,S. Tyagi,M. Bohr,Y. El-Mansy +27 more
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Journal ArticleDOI
Fabrication and analysis of deep submicron strained-Si n-MOSFET's
TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Journal ArticleDOI
A simple theory to predict the threshold voltage of short-channel IGFET's
TL;DR: A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects in this paper, which is valid for short and long-channel lengths.