Journal ArticleDOI
Hot-electron-induced MOSFET degradation—Model, monitor, and improvement
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TLDR
In this paper, a physical model involving the breaking of the ≡ Si s H bonds was proposed to explain the observed time dependence of MOSFET degradation and the observed channel field.Abstract:
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.read more
Citations
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Journal ArticleDOI
Short-channel effects in SOI MOSFETs
S. Veeraraghavan,Jerry G. Fossum +1 more
TL;DR: In this article, a short-channel effect exclusive to thin-film silicon-on-insulator (SOI) MOSFETs, back-surface charge modulation, is described.
Journal ArticleDOI
Future CMOS scaling and reliability
TL;DR: In this paper, the authors reviewed the goals and constraints of MOSFET scaling and highlighted the role of reliability constraints, and concluded that judicial shrinking of device dimensions can sustain the historical trend of scaling through the 0.09-mu m (4-Gb SRAM) generation of technology, which may be used for IC production in the year 2010.
Journal ArticleDOI
Berkeley reliability tools-BERT
TL;DR: Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits.
Journal ArticleDOI
On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress
TL;DR: In this paper, a common framework for interface-trap (NIT) generation involving broken equivSi-H and equiv Si-O bonds is developed for negative bias temperature instability (NBTI), Fowler-Nordheim (FN), and hot-carrier injection (HCI) stress.
Proceedings ArticleDOI
Dynamic NBTI of PMOS transistors and its impact on device lifetime
Gang Chen,K.Y. Chuah,Meng Li,D.S.H. Chan,Chew Hoe Ang,Jia Zhen Zheng,Yunye Jin,Dim-Lee Kwong +7 more
TL;DR: In this article, the authors demonstrate that the interface traps generated under NBTI stressing in a p-MOSFET are subsequently passivated when the gate to drain voltage switches to positive (corresponding to the low output state of the inverter).
References
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Journal ArticleDOI
Problems related to p-n junctions in silicon
TL;DR: In this article, a simplified model of secondary ionization, avalanche breakdown and microplasma phenomena in p-n junctions was proposed, in which holes and electrons have identical properties described by four constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean free path L i.
Journal ArticleDOI
Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices
Kjell Jeppson,Christer Svensson +1 more
TL;DR: A detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25-125°C) and fields (400-700 MV/m) comparable to those used in MNOS devices is presented in this article.
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An empirical model for device degradation due to hot-carrier injection
E. Takeda,N. Suzuki +1 more
TL;DR: In this article, an empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented, and the relationship between device degradation, drain voltage, and substrate current is clarified on the basis of experiments and modeling.
Journal ArticleDOI
Photon Emission from Avalanche Breakdown in Silicon
A. G. Chynoweth,K. G. McKay +1 more
TL;DR: In this article, it was shown that the number of light spots increases with the current rather than individual spots growing brighter, and that all the breakdown current is carried through the junction by these localized light-emitting spots.
Journal ArticleDOI
Electrochemical Charging of Thermal SiO2 Films by Injected Electron Currents
TL;DR: In this article, a series of experiments designed to characterize the charging effect of thermal SiO2 films with water was conducted. And they found that if water is diffused into a SiO 2 film, water related centers are formed which act like electron traps with capture cross section of approximately 1.5 × 10−17 cm2.