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Journal ArticleDOI

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

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TLDR
In this paper, a physical model involving the breaking of the ≡ Si s H bonds was proposed to explain the observed time dependence of MOSFET degradation and the observed channel field.
Abstract
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.

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Citations
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Journal ArticleDOI

Time-dependent characteristics and physical mechanisms of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors under different bias conditions

TL;DR: In this article, the authors investigated the time-dependent degradation of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors subjected to different bias conditions.
Journal ArticleDOI

Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights

TL;DR: A fully CMOS-compatible multi-level non-volatile memory technology, especially suitable for storing the weights of artificial neural networks on chip with low cost, high density, and high power-efficiency is presented.
Proceedings ArticleDOI

A design reliability methodology for CMOS VLSI circuits

TL;DR: In this paper, a set of practical DFR tools and procedures have been developed and deployed to realistically manage product reliability throughout the design phase of a VLSI circuit, and these procedures manage wear-out concerns through verifying compliance of every node with all the reliability design rules.
Book ChapterDOI

Multi-level reliability simulation for IC design

TL;DR: In this article, the authors present multi-level solutions for reliability prediction in digital and analog design, including (1) device-level long-term aging models that capture unique operation patterns in digital design, (2) circuit-level simulation method for analog reliability analysis, and (3) gate-level reliability simulation for large-scale digital designs.
Proceedings ArticleDOI

A model for channel hot carrier reliability degradation due to plasma damage in MOS devices

TL;DR: In this paper, an empirical relationship between device channel hot carrier lifetime and process induced damage has been developed, by correlating the antenna ratio (AR) to the channel Hot carrier lifetime (/spl tau/) of both N- and P-MOSFETs.
References
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Journal ArticleDOI

Problems related to p-n junctions in silicon

TL;DR: In this article, a simplified model of secondary ionization, avalanche breakdown and microplasma phenomena in p-n junctions was proposed, in which holes and electrons have identical properties described by four constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean free path L i.
Journal ArticleDOI

Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices

TL;DR: A detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25-125°C) and fields (400-700 MV/m) comparable to those used in MNOS devices is presented in this article.
Journal ArticleDOI

An empirical model for device degradation due to hot-carrier injection

TL;DR: In this article, an empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented, and the relationship between device degradation, drain voltage, and substrate current is clarified on the basis of experiments and modeling.
Journal ArticleDOI

Photon Emission from Avalanche Breakdown in Silicon

TL;DR: In this article, it was shown that the number of light spots increases with the current rather than individual spots growing brighter, and that all the breakdown current is carried through the junction by these localized light-emitting spots.
Journal ArticleDOI

Electrochemical Charging of Thermal SiO2 Films by Injected Electron Currents

TL;DR: In this article, a series of experiments designed to characterize the charging effect of thermal SiO2 films with water was conducted. And they found that if water is diffused into a SiO 2 film, water related centers are formed which act like electron traps with capture cross section of approximately 1.5 × 10−17 cm2.
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