Journal ArticleDOI
Hot-electron-induced MOSFET degradation—Model, monitor, and improvement
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TLDR
In this paper, a physical model involving the breaking of the ≡ Si s H bonds was proposed to explain the observed time dependence of MOSFET degradation and the observed channel field.Abstract:
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.read more
Citations
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Proceedings ArticleDOI
Compact modeling for simulation of circuit reliability: Historical and industrial perspectives
TL;DR: In this paper, the authors provide a historical background of the first developments of compact modeling for circuit-level reliability simulation at UC Berkeley, and the subsequent implementation into the BERT reliability simulator more than 20 years ago.
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AC-DC factor sensitivity for DRAM components lifetime under hot-carrier injection
TL;DR: In this paper, the authors proposed the DC to AC lifetime ratio factor and its sensitivity over three parameters: device degradation, effective drain voltage in word-line driving circuit, and access frequency.
Proceedings ArticleDOI
Channel Hot-Carrier degradation in short channel devices with high-k/metal gate stacks
Esteve Amat,T. Kauerauf,Robin Degraeve,Rosana Rodriguez,Montserrat Nafria,Xavier Aymerich,Guido Groeseneken +6 more
TL;DR: In this paper, the channel hot-carrier degradation in short channel transistors with a high-k/metal gate stack processed in CMOS technology has been analyzed, and the most damaging stress condition has been found to be V G =V D instead of the "classical" V G + V D /2 determined for long channel Transistors.
Proceedings ArticleDOI
Hot-carrier and recovery effect on p-channel lateral DMOS
Stefano Aresu,R.-P. Vollertsen,Ralf Rudolf,Christian Schlunder,Hans Reisinger,Wolfgang Gustin +5 more
TL;DR: In this article, the effect of hot carrier stress on source drain current in high-voltage p-channel lateral DMOS transistors has been investigated and the effect has been analyzed combining experimental data and TCAD simulations.
Journal ArticleDOI
Effect of Reverse Body Bias on Hot Carrier Induced Degradation of n-MOSFETs
Laura Atzeni,Mattia Rossetti +1 more
TL;DR: In this article, the impact of the reverse body bias (RBB) on hot carrier induced degradation of n+ polysilicon gate n-channel MOSFETs is investigated.
References
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Problems related to p-n junctions in silicon
TL;DR: In this article, a simplified model of secondary ionization, avalanche breakdown and microplasma phenomena in p-n junctions was proposed, in which holes and electrons have identical properties described by four constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean free path L i.
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Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices
Kjell Jeppson,Christer Svensson +1 more
TL;DR: A detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25-125°C) and fields (400-700 MV/m) comparable to those used in MNOS devices is presented in this article.
Journal ArticleDOI
An empirical model for device degradation due to hot-carrier injection
E. Takeda,N. Suzuki +1 more
TL;DR: In this article, an empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented, and the relationship between device degradation, drain voltage, and substrate current is clarified on the basis of experiments and modeling.
Journal ArticleDOI
Photon Emission from Avalanche Breakdown in Silicon
A. G. Chynoweth,K. G. McKay +1 more
TL;DR: In this article, it was shown that the number of light spots increases with the current rather than individual spots growing brighter, and that all the breakdown current is carried through the junction by these localized light-emitting spots.
Journal ArticleDOI
Electrochemical Charging of Thermal SiO2 Films by Injected Electron Currents
TL;DR: In this article, a series of experiments designed to characterize the charging effect of thermal SiO2 films with water was conducted. And they found that if water is diffused into a SiO 2 film, water related centers are formed which act like electron traps with capture cross section of approximately 1.5 × 10−17 cm2.