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Journal ArticleDOI

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

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TLDR
In this paper, a physical model involving the breaking of the ≡ Si s H bonds was proposed to explain the observed time dependence of MOSFET degradation and the observed channel field.
Abstract
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.

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Citations
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Journal ArticleDOI

Bulk and surface degradation mode in 0.35μm technology gg-nMOS ESD protection devices

TL;DR: In this paper, failure mechanisms in 0.35μm process grounded-gate nMOS electrostatic discharge (ESD) protection devices stressed by high current - ESD like - pulses are investigated.
Proceedings ArticleDOI

New method for the parameter extraction in Si MOSFETs after hot carrier injection

TL;DR: In this paper, a new parameter extraction method is proposed for the monitoring of hot carrier injection (HCI) degradation in Si MOSFET's allowing details of the contributions of the channel and access source-drain extension regions to be obtained.
Journal ArticleDOI

Optimization of LDD devices for cryogenic operation

TL;DR: In this article, the authors studied the optimization of lightly doped drain (LDD) devices to maximize hot-carrier device lifetime at cryogenic temperature, and the degradation behavior of both LDD and non-LDD devices at 77 K does not follow the simple behavior modeled by substrate current.
Book ChapterDOI

From Atoms to Circuits: Theoretical and Empirical Modeling of Hot Carrier Degradation

TL;DR: The increase in CMOS hot carrier lifetime due to Deuterium anneals motivates a straightforward physical picture for hot carrier degradation as discussed by the authors, and various possible isotope effects provide context for a discussion of some qualitative aspects of the physics.
Proceedings ArticleDOI

Build-in reliability analysis for circuit design in the nanometer technology era

TL;DR: In this paper, the authors present the methodology of the reliability modeling and simulation for the state-of-the-art technology for HCI (Hot Carrier Injection) and NBTI (Negative Bias Temperature Instability) for both lifetime and aged model parameter method.
References
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Journal ArticleDOI

Problems related to p-n junctions in silicon

TL;DR: In this article, a simplified model of secondary ionization, avalanche breakdown and microplasma phenomena in p-n junctions was proposed, in which holes and electrons have identical properties described by four constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean free path L i.
Journal ArticleDOI

Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices

TL;DR: A detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25-125°C) and fields (400-700 MV/m) comparable to those used in MNOS devices is presented in this article.
Journal ArticleDOI

An empirical model for device degradation due to hot-carrier injection

TL;DR: In this article, an empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented, and the relationship between device degradation, drain voltage, and substrate current is clarified on the basis of experiments and modeling.
Journal ArticleDOI

Photon Emission from Avalanche Breakdown in Silicon

TL;DR: In this article, it was shown that the number of light spots increases with the current rather than individual spots growing brighter, and that all the breakdown current is carried through the junction by these localized light-emitting spots.
Journal ArticleDOI

Electrochemical Charging of Thermal SiO2 Films by Injected Electron Currents

TL;DR: In this article, a series of experiments designed to characterize the charging effect of thermal SiO2 films with water was conducted. And they found that if water is diffused into a SiO 2 film, water related centers are formed which act like electron traps with capture cross section of approximately 1.5 × 10−17 cm2.
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