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Journal ArticleDOI

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

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TLDR
In this paper, a physical model involving the breaking of the ≡ Si s H bonds was proposed to explain the observed time dependence of MOSFET degradation and the observed channel field.
Abstract
Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.

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Proceedings ArticleDOI

A phenomenon of charge trapping saturation induced by rapid thermal annealing

TL;DR: In this article, the authors investigated the impact of Rapid Thermal Annealing temperature on hot electron reliability by using DC stress measurement and found that the substrate current of sample with RTA temperature higher than 900/spl deg/C degrades with time.
Book ChapterDOI

8 – Simulation of Degradation Phenomena in Semiconductor Components in order to Ensure the Reliability of Integrated Circuits

TL;DR: In this article, the MOS transistor (metal oxide semiconductor field effect transistor) and / or the bipolar transistor are used in many applications including transport, medicine, telecommunications etc. All of these applications rely on the use of the same basic unit.
Journal ArticleDOI

Relationship between profile of stress generated interface traps and degradation of submicron LDD MOSFET'S

TL;DR: In this article, the authors showed that the saturation of the series resistance increase is due to the leveling off of the rate of interface trap generation and not to the self-limiting impact of such defects on the series resistances.
Book ChapterDOI

Channel Hot Carriers and Other Reliability Mechanisms

TL;DR: In this paper, a general study of CHC degradation in pMOSFETs is devoted to novel Ge-based devices, which suffers of a lack of literature due to the reduced relevance in standard Si technologies.
Proceedings ArticleDOI

Simulation of interface state generation effects in LDD MOSFET's

TL;DR: In this article, a two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of an LDD MOSFET after hot carrier stress.
References
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Journal ArticleDOI

Problems related to p-n junctions in silicon

TL;DR: In this article, a simplified model of secondary ionization, avalanche breakdown and microplasma phenomena in p-n junctions was proposed, in which holes and electrons have identical properties described by four constants: generation of highest energy or Raman phonons, energy E R and mean-free-path L R ; ionization or electron-hole pair production, threshold carrier energy E i and mean free path L i.
Journal ArticleDOI

Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices

TL;DR: A detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25-125°C) and fields (400-700 MV/m) comparable to those used in MNOS devices is presented in this article.
Journal ArticleDOI

An empirical model for device degradation due to hot-carrier injection

TL;DR: In this article, an empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented, and the relationship between device degradation, drain voltage, and substrate current is clarified on the basis of experiments and modeling.
Journal ArticleDOI

Photon Emission from Avalanche Breakdown in Silicon

TL;DR: In this article, it was shown that the number of light spots increases with the current rather than individual spots growing brighter, and that all the breakdown current is carried through the junction by these localized light-emitting spots.
Journal ArticleDOI

Electrochemical Charging of Thermal SiO2 Films by Injected Electron Currents

TL;DR: In this article, a series of experiments designed to characterize the charging effect of thermal SiO2 films with water was conducted. And they found that if water is diffused into a SiO 2 film, water related centers are formed which act like electron traps with capture cross section of approximately 1.5 × 10−17 cm2.
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