Journal ArticleDOI
Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits
Reads0
Chats0
TLDR
In this article, the performance improvement that several basic analogue cells can achieve when optimized in fully depleted silicon-on-insulator (SOI) CMOS, rather than in bulk CMOS technology, was investigated.Abstract:
Transistor models which reproduce the superior device characteristics of fully depleted silicon-on-insulator (SOI) MOSFETs and which are efficient for the design of analogue CMOS circuits are discussed and validated. These analogue models are then used to investigate the significant performance improvement that several basic analogue cells can achieve when optimized in fully depleted SOI CMOS, rather than in bulk CMOS technology. Experimental verifications support this original demonstration of the great potential of fully depleted SOI CMOS for low voltage, low power analogue applications.read more
Citations
More filters
Journal ArticleDOI
Influence of device engineering on the analog and RF performances of SOI MOSFETs
Valeriya Kilchytska,Amaury Nève,Laurent Vancaillie,David Levacq,Stéphane Adriaensen,H. van Meer,K. De Meyer,C. Raynaud,Morin Dehan,Jean-Pierre Raskin,Denis Flandre +10 more
TL;DR: In this paper, the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m.
Journal ArticleDOI
Fully-depleted SOI CMOS for analog applications
TL;DR: In this article, the FD SOI MOSFETs offer near-ideal properties for analog applications, in particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates.
ased Methodology for the Design of CMOS Analog Circuits and Its Application to the Synthesis of a Silicon-on-Insulator
TL;DR: In this article, a new design methodology based on a unified treat- ment of all the regions of operation of the MOS transistor is proposed for the design of CMOS analog circuits.
Journal ArticleDOI
Fully-depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems
Denis Flandre,Stéphane Adriaensen,A. Akheyar,André Crahay,Laurent Demeûs,P. Delatte,Vincent Dessard,Benjamin Iniguez,Amaury Nève,B Katschmarskyj,Pierre Loumaye,J. Laconte,I. Martinez,G. Picun,E. Rauly,Christian Renaux,D. Spôte,M Zitout,Morin Dehan,Bertrand Parvais,Pascal Simon,D. Vanhoenacker,Jean-Pierre Raskin +22 more
TL;DR: Based on an extensive review of research results on the material, process, device and circuit properties of thin-film fully depleted SOI CMOS, the authors demonstrates that such a process with channel lengths of about 1 mum may emerge as a most promising and mature contender for integrated microsystems which must operate under lowvoltage low-power conditions, at microwave frequencies and/or in the temperature range 200-350 degreesC.
Journal ArticleDOI
Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits
Denis Flandre,Jean-Pierre Colinge,J. Chen,D. De Ceuster,J.P. Eggermont,L. F. Ferreira,B. Gentinne,Paul Jespers,A. Viviani,R. Gillon,J-P Raskin,A. Vander Vorst,Danielle Vanhoenacker-Janvier,Fernando Silveira +13 more
TL;DR: In this article, the authors demonstrate that FD SOI MOSFETs exhibit near-ideal body factor, sub-threshold slope and current drive properties for mixed fabrication and operation under low supply voltage of analog, digital and microwave components.
References
More filters
Book
Operation and modeling of the MOS transistor
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Book
CMOS Analog Circuit Design
TL;DR: In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.
Book
Silicon-on-Insulator Technology: Materials to VLSI
TL;DR: In this paper, the authors present a set of techniques for defect detection in SOI materials, including the following: 2.1.1 Silicon-on-Zirconia (SOZ), 2.2.2 E-beam recrystallization, 2.3.3, 3.4.4, and 3.5.5 Other defect assessment techniques.
Journal ArticleDOI
Comparison of SOI versus bulk performances of CMOS micropower single-stage OTAs
TL;DR: In this paper, the performance of micropower single-stage CMOS OTAs implemented in SOI or bulk technologies is compared and the improvements resulting from the superior device characteristics of fully-depleted SOI MOSFETs are discussed.
Journal ArticleDOI
Comments on ''Numerical analysis of small-signal characteristics of a fully depleted SOI MOSFET
TL;DR: In this article, the authors present a numerical analysis of small-signal characteristics of a fully depleted SOI MOSFET with respect to its small signal characteristics in terms of the SOI signal.