Yan, Q., Yuan, X., Geng, Y., Charalambous, A., & Wu, X. (2017).
Performance Evaluation of Split Output Converters with SiC
MOSFETs and SiC Schottky Diodes.
IEEE Transactions on Power
Electronics
,
32
(1), 406-422.
https://doi.org/10.1109/TPEL.2016.2536643
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Transactions on Power Electronics
1
Performance Evaluation of Split Output Converters
with SiC MOSFETs and SiC Schottky Diodes
Qingzeng Yan, Xibo Yuan, Senior Member, IEEE, Yiwen Geng, Apollo Charalambous, and Xiaojie Wu, Member, IEEE
Abstract—The adoption of silicon carbide (SiC)
MOSFETs and SiC Schottky diodes in power converters
promises a further improvement of the attainable power
density and system efficiency, while it is restricted by several
issues caused by the ultra-fast switching, such as phase-leg
shoot-through (‘crosstalk’ effect), high turn-on losses,
electromagnetic interference (EMI), etc. This paper
presents a split output converter which can overcome the
limitations of the standard two-level voltage source
converters when employing the fast-switching SiC devices.
A mathematical model of the split output converter has been
proposed to reveal how the split inductors can mitigate the
crosstalk effect caused by the high switching speed. The
improved switching performance (e.g. lower turn-on losses)
and EMI benefit have been demonstrated experimentally.
The current freewheeling problem, the current pulses and
voltage spikes of the split inductors, and the disappeared
synchronous rectification are explained in detail both
experimentally and analytically. The results show that, the
split output converter can have lower power device losses
compared with the standard two-level converter at high
switching frequencies. However, the extra losses in the split
inductors may impair the efficiency of the split output
converter, which is verified by experiments in the
continuous operating mode. A 95.91% efficiency has been
achieved by the split output converter at the switching
frequency of 100kHz with suppressed crosstalk, lower turn-
on losses, and reduced EMI.
Index Terms—Silicon carbide (SiC), split output
converters, crosstalk, efficiency, electromagnetic
interference (EMI).
I. INTRODUCTION
Silicon carbide (SiC) is superior to silicon (Si) with wider
bandgap, greater electric-breakdown field strength, and higher
thermal conductivity. Compared with Si devices, the SiC
counterparts can block higher voltage, achieve higher power
density, and promise a further improvement of the attainable
system efficiency [1], [2].
The SiC MOSFETs have no tail current during switching,
which characterizes the switching of Si IGBTs, resulting in the
faster switching speed and dramatically reduced switching
losses. The adoption of SiC MOSFETs enables the converters
to operate at higher switching frequencies with reduced size and
weight of the passive filters. However, the converters with high
switching speed are more susceptible to the parasitic elements
of the power circuits, e.g. the parasitic inductance of printed
circuit board (PCB) traces and the parasitic capacitance of
switching devices [3]. High dv/dt caused by the high switching
speed can intensify the interaction between the two
complementary SiC MOSFETs of the same phase leg (crosstalk
[4]), inducing spurious gate voltage which may lead to the
shoot-through failure of the converters. Besides, the high dv/dt
and di/dt will bring more serious electromagnetic interference
(EMI) problem [5]. Another issue for the adoption of SiC
MOSFETs is that, the intrinsic body diode of the SiC MOSFET
tends to have relatively higher forward voltage drops and larger
reverse-recovery losses compared to the purpose-designed
diode. Anti-paralleling a better performance SiC Schottky diode
is preferred in some applications [6]. However, even if the anti-
parallel SiC Schottky diode features zero reverse recovery
current, its output capacitance can still increase the total parallel
capacitance of SiC MOSFETs contributing to the turn-on losses
[3].
The split output converters [7]–[9], which are also known as
the dual-buck converters [10]–[14], can transcend the above
limitations of the standard two-level converters by adding
auxiliary inductors to decouple the upper SiC MOSFET and the
lower SiC MOSFET of the same phase leg, as shown in Fig. 1.
Q
1
~Q
6
are SiC MOSFETs and D
1
~D
6
are SiC Schottky diodes;
L
load
is the load/filtering inductor. For the sake of clear
description, the auxiliary inductors in split output converters,
e.g. L
s1
and L
s4
in Fig. 1, are called the ‘split inductors’. With
different modulation strategies, there can be two operation
modes in the split output converter according to the features
without or with the synchronous rectification [10], [11]. Taking
the case where the current flows out of Phase C for example,
without the synchronous rectification, the current flowing path
will alternate between the channel of the upper SiC MOSFET
Q
5
and the lower SiC Schottky diode D
2
; with the synchronous
rectification (by turning Q
2
on), the current flowing path will
alternate between the channel of the upper SiC MOSFET Q
5
and
the lower SiC Schottky diode D
2
in parallel with the channel of
the lower SiC MOSFET Q
2
.
As seen in Fig. 1, the split inductors separate the upper SiC
MOSFET from the lower SiC MOSFET, as well as the SiC
MOSFET from its anti-parallel SiC Schottky diode (e.g. Q
1
and
D
1
), while the commutation loop remains low inductive to
guarantee the fast switching speed. Consequently, with the split
inductors the crosstalk effect will be suppressed with lower
induced spurious gate voltage avoiding the shoot-through
failure. The charging current of the output capacitance and the
This work was supported in part by the UK EPSRC National Centre for
Power Electronics under Grant EP/K035096/1 and EP/K035304/1, the Newton
Research Collaboration Programme under Project NRCP/1415/138, the
Specialized Research Fund for the Doctoral Program of Higher Education
(SRFDP) under Project 20120095110017, and the China Scholarship Council.
Q. Yan is with the Department of Electrical and Electronic Engineering,
University of Bristol, Bristol BS8 1UB, U.K., and also with the School of
Information and Electrical Engineering, China University of Mining and
Technology, Xuzhou, Jiangsu 221116, China (e-mail: yqz2009@163.com).
X. Yuan and A. Charalambous are with the Department of Electrical and
Electronic Engineering, University of Bristol, Bristol BS8 1UB, U.K. (e-mail:
xibo.yuan@bristol.ac.uk; apollo.charalambous@bristol.ac.uk) (Corresponding
author: X. Yuan).
Y. Geng and X. Wu are with the School of Information and Electrical
Engineering, China University of Mining and Technology, Xuzhou, Jiangsu
221116, China (e-mail: gengyw556@126.com; zgcumt@126.com).
This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2536643, IEEE
Transactions on Power Electronics
2
reverse recovery current of the body diode will be both
attenuated by the split inductors resulting in lower turn-on
losses of the SiC MOSFET. In addition, if regarding the nodes
O
a
, O
b
, and O
c
in Fig. 1 as the outputs of the converter, the dv/dt
of the output voltage will also be suppressed with mitigated EMI.
Q1
D1
Q4
D4
Lload
Ls1
Ls4
Q3
D3
Q6
D6
Ls3
Ls6
Q5
D5
Q2
D2
Ls5
Ls2
Lload
Lload
Cdc
Vdc
Oa
Ob
Oc
+
_
Fig. 1. Three-phase split output converter.
Regarding the study of the converters based on the split
output topology, there have been several publications focusing
on the modulation [10], [11], control [12], and extension for
specific topologies, e.g. the three-level converters [13] and the
cascade converters [14]. Meanwhile, for the high-switching-
frequency applications based on wide bandgap power devices,
the advantages of the split output converter have been generally
described in [7]. The current commutation mechanism in the
split output converter has been analyzed in [8]. And in [9], the
additional challenges, e.g. the current pulses and voltage spikes
of split inductors, have been presented. However, there is a lack
of systematic and conclusive investigation into the split output
converters regarding the crosstalk effect, the switching
performance, EMI, and the specific issues of the split output
converters, which should be concerned in high-switching-
frequency applications.
This paper therefore aims to investigate the split output
converter both experimentally and analytically and to reveal the
advantages, disadvantages, and challenges of the split output
converter in high-switching-frequency applications. The
remaining parts of this paper are structured as follows. In
Section II, the designed three-phase split output converter and
the measurement equipment are described. A mathematical
model of the split output converter is proposed in Section III, to
reveal how the value of the split inductors affects the crosstalk
caused by the high switching speed. In section IV, the improved
switching performance and EMI benefits in the split output
converter are verified by the captured switching transients. In
addition, the current freewheeling problem, the current pulses
and voltage spikes of split inductors, and the disappeared
synchronous rectification, which can together increase the
converter losses, are investigated in Section V. Based on the
measured switching losses and the conduction characteristics
from datasheets, the power device losses without and with split
inductors are calculated in Section VI. The theoretical results
from calculation indicate that, the split output converter can
have lower power device losses at high switching frequencies
compared with the standard two-level converter. However, the
experimental results of continuous operating mode in Section
VII show that, the efficiency of the split output converter is
impaired by the additional split inductor losses. Lastly in
Section VIII, the advantages, disadvantages, and challenges of
the split output converter are concluded on the basis of the study
in this paper.
II. DESIGNED SPLIT OUTPUT CONVERTER AND MEASUREMENT
EQUIPMENT
A three-phase split output converter is designed with the
scheme in Fig. 1 for the experimental study of this paper. The
top view and bottom view of the designed converter are shown
in Fig. 2. The dc-link voltage is designed as 600V, and the rated
ac line voltage is 380V (RMS). The SiC MOSFET
C2M0080120D (20A, 1200V, 80mΩ) and the SiC Schottky
diode C4D20120A (20A, 1200V) both from Cree are used. With
20% margin of the device rated current, the rated ac current of
the converter is about 11A (RMS) with a rated capacity of
7.5kVA.
Regarding the measurement equipment, a 350MHz
bandwidth 10:1 passive voltage probe with a short ground lead
is used for the gate voltage measurement. A differential voltage
probe from Agilent Technologies (N2790A, 100MHz) is
employed to measure the switching voltage. Given the non-
galvanic isolation of the coaxial shunt and the low bandwidth of
Rogowski coil [15], the split core current probe also from
Agilent Technologies (N2783A, 100MHz, 30A) is adopted for
the current measurement.
(a)
For placing
current probes
Split inductors
Gate drivers
Middle nodes
DC-link capacitors
(b)
Film capacitors for ringing minimization
SiC MOSFET
SiC Schottky diode
Fig. 2. The designed three-phase split output converter: (a) top view and (b)
bottom view.
There is a tradeoff between the convenience of the current
measurement and the low parasitic inductance of the switching
path. Square holes, as shown in Fig. 2(a), are designed on the
board for placing the current probes. While leaving enough
space for placing the current probes, the switching path is
designed with minimal length and on both sides of the PCB, to
minimize the parasitic inductance. The parasitic inductance of
the switching path between the upper and the lower power
devices is measured as 40.8nH by the Wayne Kerr 65120B
Precision Impedance Analyzer. The dc-link film capacitors
shown in Fig. 2(b) are mounted closely to the switching devices
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2536643, IEEE
Transactions on Power Electronics
3
for suppressing the current/voltage ringing generated by the
high speed switching [16]. In addition, the middle nodes shown
in Fig. 2(a) are used to connect the split inductors of various
values according to the requirements. The output voltage of the
gate driver IXDN609SI is designed as -5V/+20V. The negative
low-state gate voltage (-5V) is used to provide the margin of
preventing the potential shoot-through failure caused by the
induced spurious gate voltage. The high-state gate voltage
should be as high as possible while within the maximum rated
gate voltage, to minimize the conduction losses of SiC
MOSFETs [17], and +20V is selected.
III. CROSSTALK ANALYSIS BASED ON A PROPOSED
MATHEMATICAL MODEL OF THE SPLIT OUTPUT CONVERTER
In this section, a mathematical model of the split output
converter is proposed to analyze the crosstalk effect. How the
split inductance and the gate resistance influence the induced
spurious gate voltage and the current overshoot at the turn-on
transient will be analyzed using this model. To simplify the
analysis of the model, the parasitic inductance of the power
circuits is neglected, and only the split inductance and the
parasitic capacitance of the devices are considered. The load
capacitance is not analyzed here, though it can be added to the
model if required. Taking Phase C of the split output converter
for example, the circuit which can be used to analyze the Q
5
turn-on transient is shown in Fig. 3(a). The parameters of the
circuit are given in Table I. Note that, all the parameters except
R
g_ex
and V
dc
in Table I are obtained from datasheets, and the
highly-nonlinear parasitic capacitances in Table I are obtained
from datasheets at the voltage of 600V, which equals to the dc-
link voltage of the proposed model. The voltage source V
s
in Fig.
3(a) represents the voltage at the middle node M of the left phase
leg when Q
5
turns on. The influence of V
s
on the right phase leg
with different split inductances and gate resistances will be
analyzed in the following.
Q5
D5
Q2
D2
Ls2Ls5
Vdc
Connect loads
ds
C
SD
C
gd
C
gs
C
g
V
g_ex
R
(a)
Cdc
N
s
V
M
Oc
g_in
R
+
_
OL
R
L
I
gs
V
gs
V
SiC MOSFET
+
_
gd
1
Cs
ds
1
Cs
gs
1
Cs
s
()Vs
gs
()Vs
g
R
s
2Ls
()
L
Is
ds
()Vs
SD
(0 )V
s
+
_
dc
()Vs
SD
1
Cs
+
_
+
_
g
()Vs
+
_
gs
(0 )V
s
+
_
(b)
NM
Fig. 3. Mathematical model of the split output converter: (a) circuit for the
analysis of Q
5
turn-on transient and (b) equivalent circuit in s domain.
TABLE I
PARAMETERS OF THE MATHEMATICAL MODEL
Symbol
Parameter
Value
C
SD
Parasitic capacitance of SiC Schottky diode
80pF
C
gd
Miller capacitance of SiC MOSFET
6.5pF
C
gs
Gate to source capacitance of SiC MOSFET
943.5pF
C
ds
Drain to source capacitance of SiC MOSFET
73.5pF
R
g_in
Internal gate resistance of SiC MOSFET
4.6Ω
R
OL
Low-state output resistance of the gate driver
0.4Ω
R
g_ex
External gate resistance
Optional
V
dc
DC-link voltage
600V
The equivalent circuit of the split output converter in s
(frequency) domain is shown in Fig. 3(b), where R
g
is the total
gate resistance (R
g
=R
OL
+R
g_ex
+R
g_in
); L
s
refers to the split
inductance, L
s
=L
s5
=L
s2
; V
SD
(0
-
) and V
gs
(0
-
) are the initial voltage
on C
SD
and C
gs
, V
SD
(0
-
)=V
dc
, V
gs
(0
-
)=V
gL
(V
gL
is the low-state
gate voltage). The initial voltages on C
gd
and C
ds
can be
neglected compared to the voltages after they are fully charged
(both approximately equal to the dc-link voltage after fully
charged). To simplify the calculation, the piecewise voltage
source V
s
(s) [18] is idealized as a step function. With the node-
voltage method, selecting V
gs
(s) and V
ds
(s) as the node voltages,
the circuit shown in Fig. 3(b) can be described as
gd ds gd gs gs
g
gs
g gs
g
ds gd SD ds gd gs
s
SD
s dc SD
s
1
( ) ( )
(0 )
1
()
1
( ) ( )
2
(0 )
1
( ) ( )
2
C sV s C s C s V s
R
V
V s C s
Rs
C s C s C s V s C sV s
Ls
V
V s V s C s
L s s
(1)
where
gL
g
()
V
Vs
s
and
dc
s dc
( ) ( )
V
V s V s
s
.
The gate voltage V
gs
(s) and the drain-source voltage of the
SiC MOSFET V
ds
(s) can be derived from (1) as
gs
s ds gd SD gs g
s s g gd
ds gd SD gd gs gd
s g gd
()
1 1 1 1
( ) ( )
22
1 1 1
2
Vs
V s C s C s C s C s V s
L s L s R C s
C s C s C s C s C s C s
L s R C s
,
(2)
ds gd gs gs gs g
gd g g
1 1 1
( ) ( ) ( )V s C s C s V s C s V s
C s R R
.
(3)
The current flowing through the split inductors can be
expressed as
s ds
s
( ) ( )
()
2
L
V s V s
Is
Ls
. (4)
The corresponding time domain values can be obtained by
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Transactions on Power Electronics
4
the inverse Laplace transform. It should be noted that V
*
gs
in Fig.
3(a) is different from V
gs
when the gate drive circuit is in the
dynamic state. V
*
gs
can be derived from V
gs
using Ohm’s law.
The value of V
*
gs
can be measured outside the device to compare
with its theoretical value.
As seen in Fig. 3(a), after V
ds
rises to V
dc
, the split inductor
current I
L
will be freewheeled by the diode D
5
. At the time of
V
ds
rising to V
dc
, V
*
gs
and I
L
will reach the maximum value. This
time can be calculated by (3). Afterwards, the maximum value
V
*
gs_max
and I
L_max
at this time can be obtained from (2) and (4),
respectively. V
*
gs_max
can be taken as the induced spurious gate
voltage. And I
L_max
can partly represent the current overshoot of
the SiC MOSFET at the turn-on transient, due to the parasitic
capacitances of D
2
and Q
5
are not taken into account.
The theoretical results using the models in (2)~(4) and the
experimental results using the double pulse test (DPT) with
varying L
s
and R
g_ex
are shown in Fig. 4. L
s
=0 represents the case
where no split inductors are used (as in a standard two-level
converter). In order to minimize the influence of ringing on the
experimental results, the external gate resistance of the
switching SiC MOSFET Q
5
is selected as 33Ω which is
relatively large, to slow down the switching speed for ringing
suppression. The external gate resistance of the lower SiC
MOSFET Q
2
is selected as required, e.g. varying from 6.2Ω to
100Ω. The theoretical and experimental results generally agree
with each other. Due to some simplifications are made in the
proposed model, e.g. the parasitic inductance of the power
circuit is neglected and V
s
(s) is idealized as a step function, the
measured spurious gate voltages and current overshoots have
some discrepancies with the theoretical results.
The split inductor currents and the induced spurious gate
voltages with L
s
=0µH and L
s
=10µH (R
g_ex
=33Ω) are shown in
Fig. 5. It should be noted in Fig. 4(a), the discrepancy between
the theoretical and experimental results without split inductors
(L
s
=0µH) is mainly caused by the ringing at the top of the
measured current in Fig. 5(a). While the other experimental
results in Fig. 4(a) with split inductors match well with the
theoretical results, due to no ringing in the measured current
with split inductors as seen in Fig. 5(b).
As seen in Fig. 4(a) and Fig. 4(b), the current overshoot I
L_max
and the induced spurious gate voltage V
*
gs_max
are gradually
reduced with the increasing split inductance. The phenomena
can be simply explained as follows. Without the split inductors,
V
s
will directly charge C
ds
and C
gd
, discharge C
SD
, causing the
large current overshoot, and the charge of the Miller capacitor
C
gd
will induce the high spurious gate voltage. After the split
inductors are added, the charging/discharging processes of C
ds
,
C
gd
, and C
SD
are buffered with smaller current overshoot and
lower spurious gate voltage. Meanwhile, as seen in Fig. 4(c),
V
*
gs_max
increases with the increasing external gate resistance
R
g_ex
, which can be explained based on the generation
mechanism of the spurious gate voltage. During the charging
process of the Miller capacitor C
gd
, the charging current will
also flow through C
gs
and the resistance on the gate drive path,
as seen in Fig. 3(a). The larger gate resistance will increase the
parallel impedance of the gate resistance and C
gs
, generating
higher spurious gate voltage. Note that, even though the larger
gate resistance can slow down the switching speed with reduced
the spurious gate voltage, the increased spurious gate voltage as
analyzed above can outweigh the reduced spurious gate voltage,
making the spurious gate voltage increase with the increasing
gate resistance.
It should be also noted that, even if the low-state gate voltage
is selected as -5V in this paper, the spurious gate voltage with a
large external gate resistance and no split inductors can still be
close to the gate threshold voltage of the SiC MOSFET (V
gs(th)
=1.7V for C2M0080120D). In contrast, the split inductors can
effectively suppress the crosstalk with reduced spurious gate
voltage preventing the potential shoot-through failure. The
proposed model can be used as a reference for the selection of
the external gate resistance and the split inductance.
L
s
[µH]
(a)
18
16
14
12
10
8
6
4
2
0
0 5 10 15 2520 30
I
L_max
[A]
Experimental results
Theoretical results
(b)
V
*
gs_max
[V]
L
s
[µH]
0 5 10 15 2520 30
1
0
-1
-2
-3
-4
-5
Experimental results
Theoretical results
(c)
R
g_ex
[Ω]
0 20 40 60 80 100
V
*
gs_max
[V]
-5.0
-4.0
-4.5
-3.5
-2.5
-2.0
-3.0
-1.5
-1.0
Experimental results
Theoretical results
Fig. 4. Theoretical results from the proposed model and experimental results:
(a) I
L_max
with varying L
s
(R
g_ex
=33Ω), (b) V
*
gs_max
with varying L
s
(R
g_ex
=33Ω),
and (c) V
*
gs_max
with varying R
g_ex
(L
s
=10µH).
