Journal ArticleDOI
Two-Dimensional Analytical Drain Current Model for Double-Gate MOSFET Incorporating Dielectric Pocket
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TLDR
In this article, a dielectric pocket double-gate MOSFET is described for low-voltage low-power applications, and a complete drain current model has been developed including the channel length modulation effect.Abstract:
In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high Ion/Ioff ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications.read more
Citations
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Journal ArticleDOI
Analytical modeling of gate-all-around junctionless transistor based biosensors for detection of neutral biomolecule species
TL;DR: In this article, a nanogap-embedded gate-all-around junctionless transistor (GAA JLT) is proposed for label-free electrochemical detection of neutral biomolecule species such as Uricase, Protein, ChOx, APTES and Streptavidin.
Journal ArticleDOI
Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications
TL;DR: In this article, a double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends is reported.
Journal ArticleDOI
2-D Analytical Threshold Voltage Model for Dielectric Pocket Double-Gate Junctionless FETs by Considering Source/Drain Depletion Effect
TL;DR: In this paper, an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs) was proposed, where the channel potential function was obtained by solving 2D Poisson's equation using an evanescent mode analysis with suitable boundary conditions.
Journal ArticleDOI
Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications
TL;DR: Thermal stability of the JLDG MOSFET has been tested for operating the device over a wide range of temperatures ranging from 200K to 500K, so that the effect of temperature on the performance issues remains limited.
Journal ArticleDOI
A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects
Zeinab Ramezani,Ali A. Orouji +1 more
TL;DR: In this paper, a double-gate SOI MOSFET with insulator packets (IPs) at the junction between channel and source/drain (S/D) ends is proposed.
References
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Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Journal ArticleDOI
Generalized scale length for two-dimensional effects in MOSFETs
TL;DR: In this paper, the authors derived a new scale length for two-dimensional effects in MOSFETs and discussed its significance, and showed that the utility of higher dielectric constant gate insulators decreases for /spl epsiv/expexp/exp/spl/exp eps/exp v/expv//sub 0/>-20 and that in no event should the insulator be thicker than the Si depletion depth.
Journal ArticleDOI
Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices
Malgorzata Jurczak,Thomas Skotnicki,R. Gwoziecki,M. Paoli,B. Tormen,P. Ribot,Didier Dutartre,Stephane Monfray,J. Galvier +8 more
TL;DR: In this paper, a new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping, which is the ideal pocket architecture.
Journal ArticleDOI
On the Ability of the Particle Monte Carlo Technique to Include Quantum Effects in Nano-MOSFET Simulation
Damien Querlioz,Jérôme Saint-Martin,Karim Huet,Arnaud Bournel,V. Aubry-Fortuna,C. Chassat,S. Galdin-Retailleau,Philippe Dollfus +7 more
TL;DR: In this article, a particle-based Monte Carlo (MC) technique was used to incorporate all relevant quantum effects in the simulation of semiconductor nanotransistors, including quantization in ultrathin-body devices.