Journal ArticleDOI
Generalized scale length for two-dimensional effects in MOSFETs
TLDR
In this paper, the authors derived a new scale length for two-dimensional effects in MOSFETs and discussed its significance, and showed that the utility of higher dielectric constant gate insulators decreases for /spl epsiv/expexp/exp/spl/exp eps/exp v/expv//sub 0/>-20 and that in no event should the insulator be thicker than the Si depletion depth.Abstract:
We derive a new scale length for two-dimensional (2-D) effects in MOSFETs and discuss its significance. This derivation properly takes into account the difference in permittivity between the Si channel and the gate insulator, and thus permits an accurate understanding of the effects of using insufficiently scaled oxide or thicker higher permittivity gate insulators. The theory shows that the utility of higher dielectric constant insulators decreases for /spl epsiv///spl epsiv//sub 0/>-20, and that in no event should the insulator be thicker than the Si depletion depth. The approach is also applied to double-gated FET structures, resulting in a new more general scale length formula for them, too.read more
Citations
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Journal ArticleDOI
High-κ gate dielectrics: Current status and materials properties considerations
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Journal ArticleDOI
MoS2 transistors with 1-nanometer gate lengths
Sujay B. Desai,Sujay B. Desai,Surabhi R. Madhvapathy,Surabhi R. Madhvapathy,Angada B. Sachid,Angada B. Sachid,Juan Pablo Llinas,Juan Pablo Llinas,Qingxiao Wang,Geun Ho Ahn,Geun Ho Ahn,Gregory Pitner,Moon J. Kim,Jeffrey Bokor,Jeffrey Bokor,Chenming Hu,H.-S. Philip Wong,Ali Javey,Ali Javey +18 more
TL;DR: Molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode are demonstrated, which exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106.
Journal ArticleDOI
Graphene and two-dimensional materials for silicon technology.
Deji Akinwande,Cedric Huyghebaert,Ching-Hua Wang,Martha I. Serna,Stijn Goossens,Lain-Jong Li,H.-S. Philip Wong,H.-S. Philip Wong,Frank H. L. Koppens,Frank H. L. Koppens +9 more
TL;DR: The opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems are reviewed, and the prospects for computational and non-computational applications are considered.
References
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Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
Scaling the Si MOSFET: from bulk to SOI to bulk
R.-H. Yan,Abbas Ourmazd,K.F. Lee +2 more
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Journal ArticleDOI
Scaling theory for double-gate SOI MOSFET's
TL;DR: In this paper, a scaling theory for double-gate SOI MOSFETs is presented, which gives guidance for device design that maintains a sub-threshold factor for a given gate length.
Journal ArticleDOI
Threshold voltage model for deep-submicrometer MOSFETs
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Journal ArticleDOI
Generalized guide for MOSFET miniaturization
TL;DR: In this paper, a simple, empirical relation has been found between MOSFET parameters and the minimum channel length for which long-channel subthreshold behavior will be observed.