Showing papers on "Bandgap voltage reference published in 2017"

A Subthreshold Voltage Reference With Scalable Output Voltage for Low-Power IoT Systems

Abstract: This paper presents a subthreshold voltage reference in which the output voltage is scalable depending on the number of stacked PMOS transistors. A key advantage is that its output voltage can be higher than that obtained with conventional low-power subthreshold voltage references. The proposed reference uses native NMOS transistors as a current source and develops a reference voltage by stacking one or more PMOS transistors. The temperature coefficient of the reference voltage is compensated by setting the size ratio of the native NMOS and stacked pMOS transistors to cancel temperature dependence of transistor threshold voltage and thermal voltage. Also, the transistor size is determined considering the trade-off between diode current between n-well and p-sub and process variation. Prototype chips are fabricated in a 0.18- $\mu \text{m}$ CMOS process. Measurement results from three wafers show $3\sigma $ inaccuracy of ±1.0% from 0 °C to 100 °C after a single room-temperature trim. The proposed voltage reference achieves a line sensitivity of 0.31%/V and a power supply rejection of −41 dB while consuming 35 pW from 1.4 V at room temperature.

5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit

Abstract: Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.

A Sub-1 ppm/°C Precision Bandgap Reference With Adjusted-Temperature-Curvature Compensation

Abstract: This paper presents a precision bandgap reference with an innovative adjusted-temperature-curvature compensation circuit that obtains a good temperature coefficient (TC) over a wide temperature range. The proposed compensation circuit for enhancing the voltage accuracy of the bandgap reference combines an addition circuit, subtraction circuit, and current mirror to achieve an adjusted piecewise linear temperature current over an entire temperature range. The proposed bandgap reference was designed and fabricated using a standard Taiwan Semiconductor Manufacturing Company (TSMC) $0.18~\mu \text{m}$ 1P6M CMOS technology. Measurements on eight samples indicated that the proposed bandgap reference achieved a TC that varies from 1.67 to 10.55 ppm/° from −40 °C to 140 °C with a supply voltage of 1.8 V. The measured 547 mV reference voltage achieved a precision line regulation that is less than 0.08%/V for supply voltages between 1.3 and 1.8 V. The proposed circuit dissipated $28~\mu \text{A}$ with a supply voltage of 1.8 V, and an active area of 0.0094 mm2. The circuit was designed to operate on a low supply voltage down to 1.3 V.

Infrastructure Circuits for Lifetime Improvement of Ultra-Low Power IoT Devices

Abstract: An ultra-low power (ULP), energy-harvesting system-on-chip, that can operate in various application scenarios, is needed for enabling the trillions of Internet-of-Things (IoT) devices However, energy from the ambient sources is little and system power consumption is high Circuits and system development require an optimal use of available energy In this paper, we present circuits that can improve the energy utilization in an IoT device by providing improvements at critical points of the flow of harvested energy A boost converter circuit, that can harvest energy from 10-mV input voltage and a few nanowatt of input power, makes more harvested energy available for the IoT device A single-inductor-multiple-output buck-boost converter provides high-efficiency and low-voltage power management solution to put most of the harvested energy for system use A real time clock and ULP bandgap reference circuit significantly reduce the standby power consumption The proposed ULP circuits are developed in 130-nm CMOS technology The combined effects of these circuits and the system design technique can improve the life-time of an example IoT device by over four times in higher power consumption mode and over 70 times in ULP mode

Temperature-Compensated $\beta$ -Multiplier Current Reference Circuit

Abstract: This brief presents the new simple schematic for the temperature stable current references based on the well-known $\boldsymbol {\beta }$ -multiplier circuit. The proposed reference utilizes only four MOS transistors and two lateral PNP transistors, which are usually available in standard CMOS technologies along with one well resistor. The temperature-compensation technique has a low process dependence and needs no trimming. However, resistor trimming can be used to precisely set the output current value. The circuit implementation of the proposed technique was fabricated in a standard 0.35- ${\mu }\text{m}$ CMOS process to source a 16- ${\mu }\text{A}$ current. The digital calibration circuit allows setting of the output current in 32 100 nA-steps. The proposed current reference achieves the supply sensitivity of several %/V without the use of the external bandgap voltage reference for the supply regulation. The measured temperature coefficient is 105 ppm/°C over the temperature range from 0 to 110 °C.

A Power-Efficient Reconfigurable Output-Capacitor-Less Low-Drop-Out Regulator for Low-Power Analog Sensing Front-End

Abstract: A power efficient reconfigurable output-capacitor-less (OCL) low-drop-out (LDO) voltage regulator for low-power analog sensing front-end is proposed in this paper. This LDO consists of a floating-gate n MOS pass transistor, an adaptively biased error amplifier, and capacitive circuits for voltage reference generation and for feedback sensing. The error amplifier adopts a class-AB input differential pair and an adaptively biased regulated cascode topology to improve transient response under the stringent constraint of low quiescent current consumption. The reference voltage is implemented by programming charges on capacitors without employing a bandgap circuit. A prototype chip is designed and fabricated in a 0.35 $\mu\text{m}$ CMOS process to demonstrate the reconfigurability and to validate the performance. The output voltage can be programmed in continuum in the range of 1.2 V to 2.5 V with measured temperature coefficients less than 45 $\text{ppm}/^{\circ}\text{C}$ . The maximum load current is designed to be 1 mA with output voltage drop less than 0.1%. With programmable quiescent current levels less than 1 $\mu\text{A}$ , the current efficiency is higher than 99.9%. From measurements, the line regulation is 0.17 mV/V or $-$ 75 dB. The designed OCL LDO remains stable with maximum output load capacitance up to 1 nF under the zero load condition.

A Low-Noise Output Capacitorless Low-Dropout Regulator With a Switched-RC Bandgap Reference

Abstract: Low-noise linear regulators are critical for power supply regulation of noise-sensitive circuits, such as ADCs, phaselocked loops, and other mixed-signal/RF system-on-a-chip designs. A low-noise low-dropout (LN-LDO) regulator using switched-RC bandgap reference and a multiloop, unconditionally stable error amplifier for output capacitorless operation is presented in this paper. A sample-and-hold switched-RC filter is developed to reduce the noise of the bandgap reference and drain-side modulated current-mode chopping technique is proposed to reduce the flicker (1/f) noise of the error amplifier. A switched capacitor notch filter is utilized to filter out the residual chopping ripple of the error amplifier. Thermal noise of the current reference circuit which is significant at such low noise levels is also reduced by using a low-area penalty passive RC filter. These techniques reduce the total integrated output noise of the LDO in the 10 Hz to 100 kHz band from 95.3 μV RMS down to 14.8 μV RMS . The LDO delivers a maximum load current of 100 mA with a dropout voltage of 230 mV and a quiescent current consumption of 40 μA. It achieves a power supply rejection of 50 dB at 10 kHz for a programmable output voltage range of 1-3.3 V. Fabricated in a 0.25 μm CMOS process, the LDO core occupies an area of 0.18 mm 2 .

A Microwatt Low Voltage Bandgap Reference for Bio-medical Applications

Abstract: In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area.

A 0.4-V Supply Curvature-Corrected Reference Generator With 84.5-ppm/°C Average Temperature Coefficient Within −40 °C to 130 °C

Abstract: This brief describes a low-power current-mode voltage reference based on subthreshold transistors. A novel circuit configuration together with a high-order temperature compensation scheme allow this voltage reference to operate with a supply voltage down to 0.4 V over a large temperature range (from −40 °C to 130 °C). The circuit, which is fabricated with a standard 0.18- $\mu\text{m}$ CMOS technology, provides an output voltage of 212 mV, while consuming 192 nW. The measured average temperature coefficient is 84.5 ppm/°C.

A 58-ppm/°C 40-nW BGR at Supply From 0.5 V for Energy Harvesting IoT Devices

Abstract: This brief presents a 40-nW 0.5-V supply voltage and 0.24-V output reference for an energy harvester. The emitter–base voltage of a PNP transistor is divided by the presented switch capacitor circuit to obtain the low output reference. The resistorless proportional-to-absolute-temperature circuit and the low-voltage high-power-supply-rejection-ratio current source are used to improve the accuracy and line regulation performance of the reference. The proposed bandgap reference is implemented in a 0.18- $\mu\text{m}$ standard complementary metal–oxide–semiconductor process and has a total area of 0.058 mm2. Test results show that the minimum supply voltage is 0.5 V due to the clock bootstrap and $2\times\text{VDD}$ doubler. The line regulation is about 1.1 mV/V in the supply voltage range of 0.5–0.9 V. With 3-bit trimming, the temperature coefficient of 58 ppm/°C in the range of −25 °C–85 °C and the accuracy of 0.9% $(3\delta)$ can be achieved.

A ± 3 ppm/°C Single-Trim Switched Capacitor Bandgap Reference for Battery Monitoring Applications

Abstract: A precision bandgap reference has been developed in a $0.18~\mu \text {m}$ BiCMOS process that achieves ±3 ppm/°C temperature drift at ±3 $\sigma $ from −40 °C to 110 °C. The reference is designed to utilize single temperature trim and standard components. A 3.65 V switched capacitor reference voltage is provided to a $2^{{\textrm {nd}}}$ order delta-sigma modulator ADC to digitize a battery cell voltage. The switched capacitor reference utilizes fully differential sampling which reduces the errors from channel charge injection and clock feedthrough introduced by pseudo-differential sampling. A new technique for sampling a $\text {V}_{{\textrm {be}}}$ voltage directly onto the output of the reference’s differential amplifier has been developed that removes the error that would be introduced from differentially sampling the $\text {V}_{{\textrm {be}}}$ and the $\Delta \text {V}_{{\textrm {be}}}$ voltage terms independently. The bandgap reference and ADC combination have an input referred noise spectral density of $4.7~\mu \text {V}/\surd $ Hz from 0.1 to 162 Hz yielding 15 stable output bits.

A 0.8V, 37nW, 42ppm/°C sub-bandgap voltage reference with PSRR of −81dB and line sensitivity of 51ppm/V in 0.18um CMOS

Abstract: This paper presents a low-power, high-PSRR sub-bandgap voltage reference that operates under 1V supply. In order to achieve low temperature coefficient (TC), a CTAT circuit with internal feedback and a two-transistor PTAT circuit are proposed. For improved line sensitivity (LS) and PSRR, a self supply-regulated feedback is employed. Implemented in 0.18μm CMOS, the proposed voltage reference achieves an average TC of 42ppm/°C, PSRR of −81dB and LS of 51ppm/V while consuming 37nW at 0.8V supply.

A 17.4-b Delta-Sigma Capacitance-to-Digital Converter for One-Terminal Capacitive Sensors

Abstract: In this brief, we present a capacitance-to-digital converter (CDC) for one-terminal capacitive sensors. The designed CDC implements a digital correction technique to reduce nonidealities and noises, such as the offset, 1/f noise, and power supply noise. This correction technique can also minimize effectively the complexity of the analog front-end circuit. All sensor functions, including analog circuits (delta-sigma CDC, bandgap reference, and voltage regulator) and digital logics (microprocessor, memories, and interface logics), are integrated into a single chip and occupy approximately 90% of the area. The chip is fabricated in a 0.18- $\mu\mbox{m}$ standard CMOS process, which does not have a deep n-well stage. The analog and digital circuits, including the digital input/output pads, must share the same substrate in this design. However, the measurement results demonstrate highly effective resolutions of 16 to 17.4 b, which are achieved with different conversion times.

A sub-1 V, nanopower, ZTC based zero-VT temperature-compensated current reference

Abstract: A nano-ampere current reference with temperature compensation operating is presented The reference current is generated biasing a zero-VT transistor near its Zero-temperature coefficient (ZTC) point Two versions were implemented in a 180 nm CMOS process Both are designed using the same thermal compensation principle, but the second version uses an auxiliary circuit to compensate process variation The circuits occupy 001 and 0018 mm2 of silicon area while consuming around 305 and 122 nW at 27° C, respectively Post-layout simulations present a reference current of 1086 and 1095 nA with a average temperature coefficient of 108 and 127 ppm/°C (100 Samples), under a temperature range from −20 to 120 °C, and a line sensitivity of 054 and 086 %/V at 09 V to 18 V of supply voltage, respectively

Electrically Tunable Energy Bandgap in Dual-Gated Ultra-Thin Black Phosphorus Field Effect Transistors

Abstract: The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus (BP) by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10 V/nm to 0.83 V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronics, thermoelectric power generation and thermal imaging.

A 0.7 V, 2.7 μW, 12.9 ppm/° C over 180° C CMOS subthreshold voltage reference

Abstract: Summary An all-CMOS, low-power, wide-temperature-range, curvature-compensated voltage reference is presented. The proposed topology achieves a measured temperature coefficient of 12.9 ppm/°C for a wide temperature range of 180°C ( − 60 to 120°C) at a bias voltage of 0.7 V while consuming a mere 2.7 μW. The high-order curvature compensation, which leads to a low-temperature sensitivity of the reference voltage, is performed using a new, simple, but efficient methodology. The non-linearities of an N-type metal-oxide-semiconductor (NMOS) device operated in subthreshold are combined with the non-linearities of two different kinds of polysilicon resistors, leading to the improved performance. The extended temperature range of this voltage reference gives it an important competitive advantage, especially at lower temperatures, where prior art designs' performance deteriorate abruptly. In addition, it utilizes an innovative trimming methodology whereby two trimmable resistors enable the tuning of both the overall slope and non-linearities of the temperature sensitivity. The design was fabricated using TowerJazz Semiconductor's CMOS 0.18 μm technology, without using diodes or any external components such as compensating capacitors. It has an area of 0.023 mm2 and is suitable for high-performance power-aware applications as well as applications operating in extreme temperatures. Copyright © 2016 John Wiley & Sons, Ltd.

A low leakage retention LDO and leakage-based BGR with 120nA quiescent current

Abstract: This paper proposes a low leakage (LL) Low-Dropout (LDO) regulator. To reduce the power consumption and skip the requirement of BJT transistors a leakage-based Bandgap Reference (BGR) is applied in this structure. To reduce the current consumption, the devices in this structure are designed to operate in sub-threshold regions. The proposed LL LDO is verified in a 55-nm CMOS process with a 0.11-mm2 active area. The quiescent current of this structure is 120nA from a 3.3 V supply voltage.

Nanopower, Sub-1 V, CMOS Voltage References With Digitally-Trimmable Temperature Coefficients

Abstract: Two variants of a MOS-only voltage reference are proposed. They are based on MOSFETs operating at a constant inversion level which cancels out nonlinearities of their temperature dependence arising from that of mobility. The theory behind the circuits is thoroughly discussed, a design method is described and experimental results are presented. The two architectures propose different trimming methods for the temperature slope of the references. A test chip was designed and fabricated on a standard $0.35~\mu \text {m}$ CMOS technology including both architectures. They generate reference voltages around 710 mV, operating from 0.9 V to 3 V supply voltage while consuming 3.0 nA and 3.3 nA. The measured temperature coefficients ranged from 8 to 40 ppm/°C in the - 20 °C to 80 °C range.

Design of an improved bandgap reference in 180nm CMOS process technology

Abstract: This paper grants implementation and design of Bandgap reference circuit with 0.2ppm/ low temperature coefficient in 180nm CMOS process technology. The designed circuit achieves a simulated output voltage reference of 1.12V at room temperature (27°C) with the temperature range of −40°C to +125°C under supply voltage of 1.8V. The power consumption is 52.37uW at room temperature and active area is 81.4um∗63.43um. The designed circuit was implemented using Cadence Virtuoso and simulated using Spectre ADE.

A GaN HEMTs half-bridge driver with bandgap reference comparator clamping for high-frequency DC-DC converter

Abstract: This paper presents a high-frequency half-bridge driver for GaN HEMTs with bandgap reference comparator clamping (BGRCC). Due to the characteristics of GaN HEMTs, the high-side supply voltage must be clamped to prevent it from exceeding the voltage limits in half-bridge configuration. The BGRCC scheme is simple and effective with low power consumption, which can adaptively keep the high-side supply voltage at an appropriate level. And the drive circuit for GaN HEMTs is specially designed and optimized to acquire low propagation delay as well as excellent mismatching delay. The simulation results show that the BGRCC scheme can clamp the high-side supply voltage at an average of 5.37 V with acceptable ripples and the maximum propagation delay for the drive circuit is around 22.6 ns when the switching frequency varies from 1 MHz to 10 MHz.

A Sub-1 V, 120 nW, PVT-Variation Tolerant, Tunable, and Scalable Voltage Reference With 60-dB PSNA

Abstract: This paper presents a novel low-power process, voltage and temperature (PVT)-variation tolerant voltage reference generator that can be easily redesigned across various CMOS technologies. The proposed circuit architecture can be used in standalone analog integrated circuits that may not require nano-scale technologies as well as system-on-a-chip applications that need analog circuits in a much lower technology node due to their dominant digital counterparts. The reference generator implements weighted averaging of a PTAT (proportional to absolute temperature) and a CTAT (complementary to absolute temperature) voltage at zero temperature coefficient (ZTC) point. PVT-variation tolerant behavior is achieved by using an on-chip shift register based switching circuit that adjusts the bias current of a key transistor in the circuit. The proposed reference generator is fabricated in 180 nm mixed-mode CMOS technology and also designed in 65 and 28 nm technologies using foundry provided models. For a temperature range from ${\mathbf 0}$ to 75 °C at 1.8 V supply, the measured tuned output voltage varies by only ${\pm 0.33}$ % across ${\mathbf 17}$ chips, which is significantly lower than all previously reported works.

Reference voltage circuit

Abstract: A reference voltage circuit is provided, which includes bandgap reference circuit, bias current generator, first capacitor, second capacitor, comparator and control logic circuit. In the active mode of the control logic circuit, the control logic circuit controls the bandgap reference circuit to deliver bandgap reference voltage. The comparator transmits first comparison signal to control logic circuit when the first and second capacitors are charged to the bandgap reference voltage. The control logic circuit enters low power mode and controls the bandgap reference circuit to stop delivering the bandgap reference voltage. If the comparator detects the potential difference between the first capacitor and second capacitor exceeds the threshold value, the control logic circuit returns to active mode according to the second comparison signal transmitted form the comparator.

High Accuracy, Multi-output Bandgap Reference Circuit in 16nm FinFet

Abstract: A CMOS bandgap reference (BGR) circuit with low mismatch spread is proposed. A conventional BGR circuit uses a CMOS error amplifier and its input offset causes large spread in the bandgap output voltage. The proposed BGR circuit does not use a separate error amplifier. Instead, the bipolar transistor pair used to generate ΔVbe acts as input differential pair as well resulting in low mismatch spread. It can generate the typical 1.22V as well as any number of less than 1.22V bandgap outputs simultaneously without requiring a separate voltage divider circuit. As compared to other offset reduction techniques such as chopping which require a clock and extra area, the proposed BGR circuit is very simple to implement. The proposed BGR circuit has been designed in 16nm FinFet technology for a wide temperature range of -40°C to 125°C and supply voltage range of 1.8V ± 10%. The post-layout extracted simulation results and silicon characterization results are in close agreement. The silicon results show that the maximum peak to peak variation is 8mV or 1.3% for a bandgap output of 0.605V. The proposed BGR consumes 340µW power at 1.8V.

Phase-cut pre-regulator and power supply comprising the same

Abstract: A power supply includes a phase-cut pre-regulator. The phase-cut pre-regulator comprises a switching device connected between a line voltage and an input voltage of a bulk capacitor and a comparator receiving the line voltage and a reference voltage, comparing the line voltage with hysteresis reference voltages based on the reference voltage, and switching the switching device according to the compared result.

A 1.2 V bandgap reference with an additional 29.6 ppm/°C temperature stable output current

Abstract: This paper presents a precise 1.175 V voltage reference bandgap circuit with an additional temperature compensated current output for DC-DC switch mode converters. The nominal temperature coefficient (TC) of the bandgap voltage is 13 ppm/°C from −40 °C to 140 °C. With the proposed circuit architecture output voltage deviations as low as ±18 mV (±3 s) from the nominal bandgap voltage are achieved. The reference output current measures 1 μA with a temperature stability of 29.6 ppm/°C. The circuit is designed in a 0.18 μm HV-CMOS process to operate from a 1.8 V supply voltage with a simulated overall current consumption of approximately 50 μA. The proposed bandgap reference circuit occupies a silicon die area of 0.05mm2.

High-temperature characterisation and analysis of leakage-current-compensated, low-power bandgap temperature sensors

Abstract: This paper analyses leakage current compensation techniques for low-power, bandgap temperature sensors. Experiments are conducted for circuits that compensate for collector-substrate, collector-bas ...