Showing papers on "Breakdown voltage published in 1996"

Very high breakdown voltage and large transconductance realized on gan heterojunction field effect transistors

Abstract: We report record high breakdown voltages up to 340 and 230 V realized on unintentionally doped (1.5 μm gate length) and Si doped (1 μm gate length) AlGaN/GaN modulation doped field effect transistors (MODFETs), respectively. The devices also have large transconductances up to 140 mS/mm and a full channel current of 150–400 mA/mm. The Si doped MODFET sample demonstrated a very high room temperature mobility of 1500 cm2/Vs. With these specifications, GaN field effect transistors as microwave power devices are practical.

Soft breakdown of ultra-thin gate oxide layers

Abstract: The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin gate oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin gate oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner oxides so that thermal effects are avoided during the breakdown of the ultra-thin oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin gate oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin oxides are compared. It is shown that for accurate ultra-thin gate oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.

Nanostructure multilayer dielectric materials for capacitors and insulators

Abstract: A capacitor is formed of at least two metal conductors having a multilayer dielectric and opposite dielectric-conductor interface layers in between. The multilayer dielectric includes many alternating layers of amorphous zirconium oxide (ZrO 2 ) and alumina (Al 2 O 3 ). The dielectric-conductor interface layers are engineered for increased voltage breakdown and extended service life. The local interfacial work function is increased to reduce charge injection and thus increase breakdown voltage. Proper material choices can prevent electrochemical reactions and diffusion between the conductor and dielectric. Physical vapor deposition is used to deposit the zirconium oxide (ZrO 2 ) and alumina (Al 2 O 3 ) in alternating layers to form a nano-laminate.

Variations in I-V characteristics of oxide semiconductors induced by oxidizing gases

Abstract: Current (I)-voltage (V) characteristics of porous sintered discs of semiconductive ZnO- and SnO2-based materials have been investigated in air, 100 ppm NO2, 800 ppm O3 and 1 H2 in the temperature range 200–700°C. All the oxide discs tested exhibited nonlinear I-V characteristics of varistor-type in every atmosphere. The breakdown voltage shifted to a high electric field upon exposure to NO2 and O3, compared with that in air, presenting a striking contrast to the behavior in 1.0% H2. It was revealed that pure ZnO and SnO2 themselves exhibited a relatively large shift in breakdown voltage when exposed to the oxidizing gases. Addition of Bi2O3 to SnO2 resulted in a slight increase in the sensitivity to NO2 and O3 but in a relatively large increase in the H2 sensitivity at 600°C. It was also found that the breakdown voltage increased with increasing the sweep rate of the electric field, suggesting some influence of the Joule's heating of a specimen during measurement on the I-V characteristics at slow sweep rates. However, the magnitude of the gas-induced shift in breakdown voltage was not so affected by the sweep rate, but rather increased at 12.3 V s−1. From these results, it was confirmed that the behavior of chemisorbed species on the surface of oxide particles near grain boundaries determined by the height of the double Schottky barrier and then the gas-sensitive non-linear I-V characteristics.

Electric breakdown in gan p-n junctions

Abstract: Electric breakdown in GaN p‐n junctions was investigated. GaN p+‐p‐n+ structures were grown on 6H–SiC substrates by metalorganic chemical vapor deposition. Mg and Si were used as dopants. Mesa structures were fabricated by reactive ion etching. Capacitance–voltage measurements showed that the p‐n junctions were linearly graded. The impurity gradient in the p‐n junctions ranged from 2×1022 to 2×1023 cm−4. Reverse current–voltage characteristics of the p‐n junctions were studied in the temperature range from 200 to 600 K. The diodes exhibited abrupt breakdown at a reverse voltage of 40–150 V. The breakdown had a microplasmic nature. The strength of the electric breakdown field in the p‐n junctions depended on the impurity gradient and was measured to be from 1.5 to 3 MV/cm. It was found that the breakdown voltage increases with temperature. The temperature coefficient of the breakdown voltage was ∼2×10−2 V/K.

Compact active quenching circuit for fast photon counting with avalanche photodiodes

Abstract: A compact and flexible circuit for operating avalanche photodiodes in Geiger mode was designed, fabricated, and tested. A new voltage driver stage, based on fast n‐channel double‐diffused metal–oxide–semiconductor (DMOS) transistors in a bootstrap configuration, makes it possible to obtain quenching pulses up to 25 V amplitude and fast active reset of the detector. At 20 V excess bias voltage above the photodiode breakdown level, an overall deadtime shorter than 36 ns is attained. The avalanche pulse charge is minimized by means of a mixed passive–active quenching approach, thus reducing self‐heating and afterpulsing effects in the photodiode. A user‐controllable hold‐off time is available for further reducing the afterpulsing effect. The saturated counting rate of the circuit exceeds 25 Mcounts/s, but, by working with avalanche photodiodes with high breakdown voltage (250–400 V) and high avalanche current (10–40 mA), a practical limit is set at about 9 Mcounts/s by thermal effects in the detector. Gated‐detector operation with gate times down to 10 ns is provided. The suitability of the new active‐quenching circuit for the development of compact, all‐solid‐state instruments for high‐performance photon counting was verified in experimental tests.

Semiconductor device having high breakdown voltage and method of manufacturing the same

Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n 31 silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Schottky barrier rectifiers and methods of forming same

Abstract: A Schottky rectifier (10) includes MOS-filled trenches and an anode electrode at a face of a semiconductor substrate and an optimally nonuniformly doped drift (12d) region therein which in combination provide high blocking voltage capability with low reverse-biased leakage current and low forward voltage drop. The nonuniformly doped drift (12d) region contains a concentration of first conductivity type dopants therein which increases monotonically in a direction away from a Schottky rectifying function formed between the anode electrode (18) and the drift region (12d). A profile of the doping concentration in the drift region is preferably a linear or step graded profile with a concentration of less than about 5x1016 cm-3 (e.g., 1x1016 cm-3) at the Schottky rectifying junction and a concentration of about ten times greater (e.g., 3x1017 cm-3) at a junction between the drift region (12d) and a cathode region (12c). The thickness of the insulating regions (16) (e.g., SiO?2?) in the MOS-filled trenches is also greater than about 1000 A to simultaneously inhibit field crowding and increase the breakdown voltage of the device. The nonuniformly doped drift region (12d) is preferably formed by epitaxial growth from the cathode region (12c) and doped in-situ.

Breakdown walkout in pseudomorphic HEMT's

Abstract: In this work we show for the first time evidence of gate-drain breakdown walkout due to hot electrons in pseudomorphic AlGaAs-InGaAs-GaAs HEMTs (PHEMTs). Experiments performed on passivated commercial PHEMTs show that hot electron stress cycles induce a large and permanent increase of the gate-drain breakdown voltage. Three-terminal and two-terminal stress conditions are compared, the former producing a much larger walkout due to hot electrons flowing in the channel. Experimental results indicate that a build-up of negative charge in the region between gate and drain is responsible for the breakdown walkout, due to a local widening of the depletion region and a reduction of the peak electric field.

Enhanced dielectric-wall linear accelerator

Abstract: A dielectric-wall linear accelerator is enhanced by a high-voltage, fast e-time switch that includes a pair of electrodes between which are laminated alternating layers of isolated conductors and insulators. A high voltage is placed between the electrodes sufficient to stress the voltage breakdown of the insulator on command. A light trigger, such as a laser, is focused along at least one line along the edge surface of the laminated alternating layers of isolated conductors and insulators extending between the electrodes. The laser is energized to initiate a surface breakdown by a fluence of photons, thus causing the electrical switch to close very promptly. Such insulators and lasers are incorporated in a dielectric wall linear accelerator with Blumlein modules, and phasing is controlled by adjusting the length of fiber optic cables that carry the laser light to the insulator surface.

High voltage termination with buried field-shaping region

Abstract: A semiconductor device structure and method are presented for increasing a breakdown voltage of a junction between a substrate of first conductivity type and a device region. The structure includes a region of second conductivity type in the substrate completely buried in the substrate below and separated from the device region. The region of second conductivity type is located a predetermined distance away from the device region. The distance is sufficient to permit a depletion region to form between the region of second conductivity type and the device region, when a first voltage is applied between the device region and the substrate. The distance also is determined to produce a radius of curvature of the depletion region, when a second voltage that is larger than the first voltage is applied between the device region and the substrate, that is larger than a radius of curvature of the depletion region about the device region that would be formed if the region of second conductivity type were not present. Traditional field shaping regions spaced from the device region at a surface of the substrate and spaced from the region of second conductivity type may be used in conjunction with the buried ring, if desired.

A critical look at the performance advantages and limitations of 4H-SiC power UMOSFET structures

Abstract: A realistic performance projection of 4H-SiC UMOSFET structures based on electric field in the gate insulator consistent with long-term reliability of insulator is provided for the breakdown voltage in the range of 600 to 1500 V. The use of P/sup +/ polysilicon gate leads to higher breakdown voltage as the Fowler Nordheim injection from the gate electrode is reduced. It is concluded that the insulator reliability is the limiting factor and therefore the high temperature operation of these devices may not be practical.

Anodized aluminum substrate having increased breakdown voltage

Abstract: There is provided an anodizable aluminum substrate having an increased breakdown voltage. The increase in breakdown voltage is achieved by selecting an appropriate aluminum alloy and appropriate processing parameters. Sealing the anodic film increases the breakdown voltage by decreasing corrosion. A preferred sealant is an epoxy cresol novolac having a low room temperature viscosity that cures to a highly cross-linked polymer.

AlInAs/GaInAs/InP double heterojunction bipolar transistor with a novel base-collector design for power applications

Abstract: We report the performance of an AlInAs/GaInAs/InP DHBT with a new collector design. The base-collector junction was formed with an all arsenide chirped superlattice with linear variation in the average composition. A doping dipole was inserted at the ends of the superlattice to cancel the quasielectric field. The conduction band offset between AlInAs and InP enabled hot electrons to be launched into the InP collector. The new design resulted in an excellent combination of speed and breakdown voltage with superior microwave power performance at X-band. Output power of 2 W (5.6 W/mm) with 70% power-added-efficiency at 9 GHz was achieved.

High voltage protection circuits

Abstract: Integrated circuits are provided for protecting a device from high voltage signals, such as caused by ESD, at an external pin (12) of a device on an integrated circuit. A first circuit has a voltage reference terminal (24), and a pin resistor (13) connected in series with the pin (12) and an input terminal (14) to a functional circuit. An SCR (30) has an anode, cathode, anode-gate, and cathode-gate terminals. The anode of the SCR (30) is connected to the input terminal, while the cathode of the SCR is connected to the voltage reference terminal (24). A shunt resistor (19) connects across the anode and anode-gate of the SCR (30), and an another shunt resistor (20) connects across the cathode and cathode-gate of the SCR. A zener diode (22) is provided for setting a breakdown voltage of the SCR (30) between its anode-gate and cathode-gate. This integrated circuit protects a device against high voltages having a positive polarity, and also protects the device from ESD voltages having a negative polarity by switching the anode connections with the cathode connections. In operation, the SCR (30) triggers in response to a voltage at the pin (12) above the zener's breakdown voltage, and the SCR automatically turns off when the voltage across the pin resistor (13) has returned to within a hold voltage level that may be near or within the operational range of signals at the pin. The relative size of the first resistor (13) and the one of shunt resistors (19 or 20) having the lowest resistance controls the holding current of the SCR at either the anode-gate or cathode-gate of the SCR (30). Another integrated circuit provides for protecting a device from high voltage signals having either a positive or negative polarity using two SCRs (28a, 28b).

Silicon carbide switching devices having near ideal breakdown voltage capability and ultralow on-state resistance

Abstract: A silicon carbide switching device having near ideal electrical characteristics includes an electrical insulator with an electrical permittivity greater than about ten times the permittivity of free space (e o ) and more preferably greater than about fifteen times the permittivity of free space, as a gate electrode insulating region. The use of electrical insulators having high electrical permittivities relative to conventional electrical insulators such as silicon dioxide significantly improves the breakdown voltage and on-state resistance characteristics of a silicon carbide switching device to the point of near ideal characteristics, as predicted by theoretical analysis. Thus, the preferred advantages of using silicon carbide, instead of silicon, can be more fully realized. Electrical insulators having low critical electric field strengths relative to conventional electrical insulators such as silicon dioxide can also be used even though these insulators are relatively more susceptible to field induced dielectric breakdown for a given electric field strength. Such electrical insulators include titanium dioxide.

SiC semiconductor device

Abstract: A semiconductor device structure having an epitaxial layer, formed of silicon for example, is disposed on a high band-gap material, such as silicon carbide, which is in turn disposed on a semiconductor substrate, such as silicon. The high band gap material achieves a charge concentration much higher than that of a conventional semiconductor material for the same breakdown voltage.

Low-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFETs

Abstract: An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 /spl mu/m SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems.

Ultrafast pulse generation in photoconductive switches

Abstract: Carrier and field dynamics in photoconductive switches are investigated by electrooptic sampling and voltage-dependent reflectivity measurements. We show that the nonuniform field distribution due to the two-dimensional nature of coplanar photoconductive switches, in combination with the large difference in the mobilities of holes and electrons, determine the pronounced polarity dependence. Our measurements indicate that the pulse generation mechanism is a rapid voltage breakdown across the photoconductive switch and not a local field breakdown.

Accelerated testing of SiO/sub 2/ reliability

Abstract: This paper compares several popular accelerated test methods for projecting SiO/sub 2/ lifetime distribution or failure rate: constant-voltage and constant-current time-to-breakdown and charge-to-breakdown tests, ramp-voltage breakdown test, and ramp-current charge to-breakdown test. Charge trapping affects the electric field acceleration parameter for time-to-breakdown and the value of breakdown voltage. Practical considerations favor ramp breakdown testing for gate oxide defect characterization. The effective thinning model is used for defect characterization and the ramp-voltage breakdown test is shown to be superior to the ramp-current Q/sub BD/ test for extraction of the defect distribution. Measurement issues are also discussed.

Dielectric-wall linear accelerator with a high voltage fast rise time switch that includes a pair of electrodes between which are laminated alternating layers of isolated conductors and insulators

Abstract: A dielectric-wall linear accelerator is improved by a high-voltage, fast rise-time switch that includes a pair of electrodes between which are laminated alternating layers of isolated conductors and insulators. A high voltage is placed between the electrodes sufficient to stress the voltage breakdown of the insulator on command. A light trigger, such as a laser, is focused along at least one line along the edge surface of the laminated alternating layers of isolated conductors and insulators extending between the electrodes. The laser is energized to initiate a surface breakdown by a fluence of photons, thus causing the electrical switch to close very promptly. Such insulators and lasers are incorporated in a dielectric wall linear accelerator with Blumlein modules, and phasing is controlled by adjusting the length of fiber optic cables that carry the laser light to the insulator surface.

A model for tunneling-limited breakdown in high-power HEMTs

Abstract: We present a new predictive model for off-state breakdown in InAlAs/InGaAs and AlGaAs/InGaAs power high electron mobility transistors (HEMTs). The proposed model suggests that electron tunneling from the gate edge, and not impact ionization, is responsible for off-state breakdown in these devices. The model indicates that the crucial variables in determining the off-state breakdown voltage of power HEMTs are the sheet carrier concentration in the extrinsic gate-drain region, and the gate Schottky barrier height. Other design parameters have only secondary impact on the breakdown voltage for realistic device designs.

Volt-time characteristics of short air gaps under nonstandard lightning voltage waves

Abstract: The breakdown voltage level of a dielectric system under a transient voltage of a given waveshape is not a constant parameter. When transient voltages of the same waveshape but of increasing amplitude are applied to a dielectric system, the dielectric breaks down at higher voltage levels at shorter time delays for the higher applied voltages. This characteristic, known as the volt-time or time-lag characteristic, significantly influences the insulation coordination of an electric power system. The volt-time characteristics of 5-cm long rod-plane and rod-rod air gaps were experimentally determined with five different waveshapes of the applied impulse voltage. The front time of the waves was varied from 25 ns to 10 {micro}s, and the time to half value was varied from 0.5 {micro}s to 100 {micro}s. The volt-time characteristics were also checked analytically using the concept of disruptive effect. The parameters for the disruptive effect were experimentally determined.

Lateral high-voltage DMOS transistor with drain zone charge draining

Abstract: In many circuits in which a current is switched off, a high voltage appears at the drain electrode of a transistor, in particular in the case of an inductive load. When a lateral high-voltage DMOST is used, such a high voltage may lead to instability in the transistor characteristics or may even damage the transistor. To avoid this problem, the drain of a high-voltage LDMOST is locally provided with a strongly doped n-type zone 18, 21 (in the case of an n-channel transistor) which extends, seen from the surface, down into the semiconductor body to a greater depth than does the source zone 8, so that a pn-junction is formed at a comparatively great depth in the semiconductor body having a breakdown voltage that is lower than the BV ds of the transistor without this zone. The energy stored in the inductance may thus be drained off through breakdown of the pn-junction. This breakdown is separated from the normal current path of the transistor owing to the comparatively great depth of the pn-junction, so that the robustness of the transistor is improved. This deep zone in the drain may be formed, for example, by a buried layer at the boundary between an epitaxial layer and the substrate.

High-field fast-risetime pulse failures in 4H- and 6H-SiC pn junction diodes

Abstract: We report the observation of anomalous reverse breakdown behavior in moderately doped (2–3×1017 cm−3) small‐area micropipe‐free 4H‐ and 6H‐SiC pn junction diodes. When measured with a curve tracer, the diodes consistently exhibited very low reverse leakage currents and sharp repeatable breakdown knees in the range of 140–150 V. However, when subjected to single‐shot reverse bias pulses (200 ns pulsewidth, 1 ns risetime), the diodes failed catastrophically at pulse voltages of less than 100 V. We propose a possible mechanism for this anomalous reduction in pulsed breakdown voltage relative to dc breakdown voltage. This instability must be removed so that SiC high‐field devices can operate with the same high reliability as silicon power devices.

Analytical approach to breakdown voltages in thin-film SOI power MOSFETs

Abstract: The breakdown voltage behavior of thin-film SOI power MOSFETs is described using an analytical approach. Simple expressions for the vertical and horizontal characteristics of the device are developed one-dimensionally to analytically predict the critical impurity concentration of the drift region and the breakdown voltages. Using this modeling, the effect of device parameters is also examined. The validity of the analytical expressions is demonstrated by comparison with the extensive results of numerical simulations.

Trench-gated power MOSFET with protective diodes in a periodically repeating pattern

Abstract: of EP0746030A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a diode that is connected in parallel with the channel region in each of the MOSFET cells. The protective diffusion, which replaces the deep central diffusion taught in U.S. Patent No. 5,072,266, prevents impact ionization and the resulting generation of carriers near the corners of the gate trench, which can damage or rupture the gate oxide layer. Moreover, the diode can be designed to have a breakdown voltage which limits the strength of the electric field across the gate oxide layer. The elimination of a deep central diffusion permits an increase in cell density and improves the on-resistance of the MOSFET.

Impulse breakdown superposed on ac voltage in XLPE cable insulation

Abstract: This paper discusses tree inception and breakdown voltage characteristics of XLPE cable insulation subjected to impulse voltages superimposed on ac voltage. The tree initiation tests were performed on laboratory-molded specimens equipped with needle electrodes, whereas the breakdown tests were conducted on a full-sized cable. The impulse tree initiation stress was found to be dependent on the magnitude of the pre-applied ac stress and the relative polarities of the impulse and the ac peak at the instant of their superposition. Although the impulse polarity has an effect on the tree inception, the general behavior is that the tree inception stress always decreases with an increase of the pre-applied ac stress. This phenomenon is discussed in terms of the space charge effect and the influence of the impulse voltage application itself. The impulse strength of a full-sized cable insulation was found to be independent of the pre-applied ac stress as long as that stress did not exceed the operating stress of a 500 kV cable insulation. However, subjecting cable insulation to higher ac stresses before impulse application caused a reduction of its breakdown strength as compared with the insulation without ac prestressing.

MOS transistor and method for making the same

Abstract: Transistor devices comprise a gate electrode, a channel region formed beneath the gate electrode, a source region in contact with one side of the channel region, a first conductive region formed in a semiconductor layer at the outer side of the source region and made of a metal or metal compound, a drain region formed in contact with the other side of the channel region, and a second conductive region formed in the semiconductor layer at the outer side of the drain region and consisting of a metal or a metal compound. The transistor has an SOI structure which has an improved breakdown voltage between the source region and the drain region with low sheet resistances of the source and drain regions. Methods for making the transistor devices are also described.