Showing papers on "Decoupling capacitor published in 2017"
TL;DR: In this article, the authors present a 2-kW, 60-Hz, 450-V -to-240-V power inverter, designed and tested subject to the specifications of the Google/IEEE Little Box Challenge, which achieves a high power density of 216 W/in $3$ and a peak overall efficiency of 97.6%, while meeting the constraints including input current ripple, load transient, thermal, and FCC Class B EMC specifications.
Abstract: High-efficiency and compact single-phase inverters are desirable in many applications such as solar energy harvesting and electric vehicle chargers. This paper presents a 2-kW, 60-Hz, 450-V $ _{\text{DC}}$ -to-240-V $_{\text{AC}}$ power inverter, designed and tested subject to the specifications of the Google/IEEE Little Box Challenge. The inverter features a seven-level flying capacitor multilevel converter, with low-voltage GaN switches operating at 120 kHz. The inverter also includes an active buffer for twice-line-frequency power pulsation decoupling, which reduces the required capacitance by a factor of 8 compared to conventional passive decoupling capacitors, while maintaining an efficiency above 99%. The inverter prototype is a self-contained box that achieves a high power density of 216 W/in $^3$ and a peak overall efficiency of 97.6%, while meeting the constraints including input current ripple, load transient, thermal, and FCC Class B EMC specifications.
251 citations
TL;DR: In this paper, a high-efficiency, high-power-density buffer architecture is proposed for power pulsation decoupling in power conversion between dc and single-phase ac. In the proposed architecture, the main energy storage capacitor is connected in series with an active buffer converter across the dc bus.
Abstract: A high-efficiency, high-power-density buffer architecture is proposed for power pulsation decoupling in power conversion between dc and single-phase ac. We present an active decoupling solution that yields improved efficiency and reduced circuit complexity compared to existing solutions. In the proposed architecture, the main energy storage capacitor is connected in series with an active buffer converter across the dc bus. The series-stacked capacitor blocks the majority of the dc bus voltage to reduce the voltage stress on the buffer converter, such that fast, low-voltage transistors can be employed for the buffer converter. Moreover, the series capacitor provides the majority of the power pulsation decoupling through a wide voltage swing, and the buffer converter only needs to process a small fraction of the total power of the entire architecture, allowing a very small active circuit volume and very high system efficiency. The circuit operation and design constraints are analyzed in detail. In the proposed buffer architecture, the series stacking of a nearly lossless capacitor and a lossy converter presents a challenge of capacitor voltage balancing and power loss compensation. We propose a control scheme exploiting the small ripple in the bus voltage and dc input current to compensate for the power loss in the buffer converter while maintaining the voltage balance. Light-load techniques are also introduced to ensure that the buffer architecture meets strict ripple requirements while providing sufficient loss compensation. A 2-kW hardware prototype based on low-voltage GaN switches has been built to demonstrate the performance of the proposed solution. A power density of 25 W/cm $^3$ (410 W/in $^3$ ) by rectangular box volume and an efficiency above 98.9% across a wide load range has been experimentally verified.
118 citations
TL;DR: In this article, a cascaded H-bridge multilevel converter (CHB-MC)-based StatCom system is proposed to operate with extremely low dc capacitance values.
Abstract: This paper introduces a cascaded H-bridge multilevel converter (CHB-MC)-based StatCom system that is able to operate with extremely low dc capacitance values. The theoretical limit is calculated for the maximum capacitor voltage ripple, and hence minimum dc capacitance values that can be used in the converter. The proposed low-capacitance StatCom ( LC -StatCom) is able to operate with large capacitor voltage ripples, which are very close to the calculated theoretical maximum voltage ripple. The maximum voltage stress on the semiconductors in the LC -StatCom is lower than in a conventional StatCom system. The variable cluster voltage magnitude in the LC -StatCom system drops well below the maximum grid voltage, which allows a fixed maximum voltage on the individual capacitors. It is demonstrated that the proposed LC -StatCom has an asymmetric V–I characteristic, which is especially suited for operation as a reactive power source within the capacitive region. A high-bandwidth control system is designed for the proposed StatCom to provide control of the capacitor voltages during highly dynamic transient events. The proposed LC -StatCom system is experimentally verified on a low-voltage seven-level CHB-MC prototype. The experimental results show successful operation of the system with ripples as high as 90% of the nominal dc voltage. The required energy storage for the LC -StatCom system shows significant reduction compared to a conventional StatCom design.
86 citations
TL;DR: Simulation and experimental studies show that CMV injection significantly reduces the capacitor voltage ripple and the CC in legs and the proposed approach also improves output voltage and current waveform quality.
Abstract: Submodule (SM) capacitor voltage ripple is one of the major concerns in modular multilevel converters (MMCs). Capacitor voltage ripple leads to the double-frequency circulating current (CC) in legs, thereby resulting in a cascading effect of increased peak value of the arm current, semiconductor device stress, and power losses in MMCs. In this study, a model predictive control (MPC) with common-mode voltage (CMV) injection is proposed to minimize capacitor voltage ripple and the magnitude of CC. A discrete-time mathematical model of the MMC with CMV is presented to predict the future behavior of the control variables. The injection of CMV guarantees arm voltage balancing without CC control and long-term stability of MMC without large capacitors. The dynamic and steady-state performances of MPC with CMV injection are verified on an MMC with three-level flying capacitor SMs. A performance comparison between the proposed approach and the conventional MPC is also presented. Simulation and experimental studies show that CMV injection significantly reduces the capacitor voltage ripple and the CC in legs. The proposed approach also improves output voltage and current waveform quality.
81 citations
01 Jul 2017
TL;DR: In this article, the authors investigated the origins of the voltage imbalance in practical implementations of flying capacitor multilevel (FCML) converters and presented corresponding solutions to solve the problem.
Abstract: Flying capacitor multilevel (FCML) converters are known to naturally balance the capacitor voltages through the use of phase-shifted pulse-width modulation. However, in practice, the capacitor voltages can still deviate and active balancing is often required. This work investigates the origins of the voltage imbalance in practical implementations of such converters and presents corresponding solutions. It is shown that the source impedance and the input capacitor can have a drastic impact on the flying capacitor voltages. Moreover, we also demonstrate that an FCML converter with an even number of levels has significantly better immunity to the presence of source impedance than one with an odd number of levels. It is also found that gate signal propagation delay mismatch from half-bridge gate drivers will lead to capacitor imbalance. An alternative gate drive power supply circuit is designed to address this problem. Lastly, variations of switches' on-resistance are found to have a small impact on the capacitor voltage balance.
75 citations
TL;DR: In this article, a photovoltaic micro-inverter with PV current decoupling (PVCD) strategy was proposed to achieve maximum power point tracking (MPPT) performance without using large electrolytic capacitors.
Abstract: The objective of this paper is to propose a novel photovoltaic (PV) micro-inverter with PV current decoupling (PVCD) strategy to achieve maximum power point tracking (MPPT) performance without using large electrolytic capacitors. Conventionally, the grid-connected PV micro-inverter needs a large PV-side electrolytic capacitor to suppress the double-line frequency voltage ripple, which is caused by the injected ac grid power, to achieve the desired MPPT performance. However, the short lifetime electrolytic capacitor will reduce the PV micro-inverter's reliability dramatically. Therefore, different active power decoupling circuits (APDCs) have been proposed in published papers to reduce the required input capacitance so that the long lifetime film capacitor can be used to replace the electrolytic capacitor. Unlike the conventional APDC with charging and discharging modes operation, a novel PVCD strategy, which is based on the concept of current decoupling instead of power decoupling, is proposed to simplify the control mechanism of the PV micro-inverter. Furthermore, to accomplish the proposed current decoupling concept, a novel circuit topology for the PV micro-inverter is also proposed. With the proposed PVCD strategy, the current decoupling tank (CDT) inside the proposed PV micro-inverter can buffer the current difference between the constant current from the PV panel and the rectified sinusoidal current of the ac grid current. Therefore, the input capacitance on the PV-side can be reduced dramatically and the long lifetime film capacitor can be used to replace the electrolytic capacitor. The reliability of the PV micro-inverter with good MPPT performance can be increased. In this paper, the operation principle and the component design of the proposed PV micro-inverter with PVCD strategy will be presented. Simulation results and experimental results of a prototype 240 W PV micro-inverter is shown to verify the performance of the PV micro-inverter with PVCD strategy.
72 citations
TL;DR: Simulation results and experimental measurements of a three-cell four-level and four-cell five-level FCM converters are presented to verify the performance of the proposed active capacitor voltage balancing control technique.
Abstract: This paper presents a new active capacitor voltage balancing control method for the flying capacitor multicell (FCM) converters which is fully implemented using logic-form equations The proposed active capacitor voltage balancing control technique, measures output current and flying capacitor (FC) voltages to generate the switching states in order to produce the required output voltage level and to balance FCs’ voltages at their reference values Output voltage of the FCM converter controlled with proposed active capacitor voltage balancing method can be modulated with any pulse width modulation (PWM) technique such as the phase-shifted-carrier PWM or level-shifted-carrier PWM An advantage of the proposed active capacitor voltage balancing control method is its simplicity as it does not require any complex computations and tedious optimization calculations Simulation results and experimental measurements of a three-cell four-level and four-cell five-level FCM converters are presented to verify the performance of the proposed active capacitor voltage balancing control technique
70 citations
26 Mar 2017
TL;DR: In this article, the authors explore the relationship among measurable circuit waveforms and flying capacitor voltage states and derive a set of sufficient conditions that ensure balance of the median capacitor voltage levels.
Abstract: This work explores the well-known challenge of achieving voltage balance of capacitors in arbitrary (N-level) flying capacitor multilevel (FCML) converters In particular, we explore the relationships among measurable circuit waveforms and flying capacitor voltage ‘states’ These are used to derive a set of sufficient conditions that ensure balance of the median capacitor voltage levels It is shown that various forms of current-limit control (eg traditional peak or valley current-mode control, or low-frequency sampled regulation of peak of valley current levels), combined with modest additional criteria, will guarantee voltage balance The concept is highlighted with a 7-level FCML converter operating with a 48 V supply, a 2 V output, and up to 10 A load current The converter uses a GaN powertrain to achieve a compact layout and low parasitics A digital control algorithm is used to regulate valley currents and the converter output voltage Valley current detection and nested low-frequency feedback regulation is highlighted in the experimental prototype
69 citations
TL;DR: In this paper, the authors proposed a two-terminal active capacitor implemented by power semiconductor switches and passive elements, which can be specified by rated voltage, ripple current, equivalent series resistance, and operational frequency range.
Abstract: This letter proposes a concept of two-terminal active capacitor implemented by power semiconductor switches and passive elements. The active capacitor has the same level of convenience as a passive one with two power terminals only. It is application independent and can be specified by rated voltage, ripple current, equivalent series resistance, and operational frequency range. The concept, control method, self-power scheme, and impedance characteristics of the active capacitor are presented. A case study of the proposed active capacitor for a capacitive dc-link application is discussed. The results reveal a significantly lower overall energy storage of passive elements and a reduced cost to fulfill a specific reliability target, compared to a passive capacitor solution. Proof-of-concept experimental results are given to verify the functionality of the proposed capacitor.
68 citations
TL;DR: This letter proposed a control method to divert DFRP to the small energy transfer capacitor, which needs no extra switches or energy storage components, which are usually required in other active power decoupling methods.
Abstract: Bulky electrolytic capacitor is usually needed in bridgeless power factor correction rectifiers to buffer the double-frequency ripple power (DFRP). However, it reduces the system reliability and power density significantly. This letter proposed a control method to divert DFRP to the small energy transfer capacitor. Then, the bulky electrolytic capacitor can be replaced with a small film capacitor. The proposed method is realized by making the best of the existing switching states. Therefore, it needs no extra switches or energy storage components, which are usually required in other active power decoupling methods. The operating principle is explained, and a closed-loop control strategy is proposed. Finally, the effectiveness is verified by experimental results.
59 citations
TL;DR: In this article, a single-stage PFC rectifier with two active switches, one inductor and one small power-buffering capacitor is proposed, which can achieve high power factor, wide output voltage range, and power decoupling function without using electrolytic capacitor.
Abstract: Conventional single-phase power-factor-correction (PFC) rectifiers with active power decoupling capability typically require more than three active switches in their circuits. By exploring the concept of power-buffer cell, a new single-stage PFC rectifier with two active switches, one inductor and one small power-buffering capacitor is reported in this paper. The proposed converter can achieve high-power factor, wide output voltage range, and power decoupling function without using electrolytic capacitor. Additionally, an automatic power decoupling control scheme that is simple and easy to implement is proposed in this paper. The operating principle, control method, and design considerations of the proposed rectifier are also provided. A 100-W prototype with ac input voltage of 110 Vrms and a regulated dc output voltage ranging from 30 to 100 V has been successfully designed and practically tested. The experimental results show that with only a 15 μ F power-buffering film capacitor, the proposed converter can achieve an input power factor of over 0.98, peak efficiency of 93.9%, and output voltage ripple of less than 3%, at 100-W output power.
TL;DR: In this article, an on-chip switched capacitor voltage regulator for granular power delivery with per-core regulation for microprocessor power delivery has been proposed, which has the potential to significantly improve the energy efficiency of future data centers.
Abstract: Granular power delivery with per-core regulation for microprocessor power delivery has the potential to significantly improve the energy efficiency of future data centers. On-chip switched capacitor converters can enable such granular power delivery with per-core regulation given a high efficiency, high power density, fast response time, and high output power converter design. This paper details the implementation of an on-chip switched capacitor voltage regulator in a $32\,\mathrm{n}\mathrm{m}$ SOI CMOS technology with deep trench capacitors. A novel feedforward control for reconfigurable switched capacitor converters is presented. The feedforward control reduces the output voltage droop following a transient load step. This leads to a reduced minimum microprocessor supply voltage, thereby reducing the overall power consumption of the microprocessor. The implemented on-chip switched capacitor voltage regulator provides a $0.7-1.1$ V output voltage from $1.8$ V input. It achieves a $85.1\%$ maximum efficiency at $3.2\,\mathrm{W}\mathrm{/}\mathrm{m}\mathrm{m}^2$ power density, a subnanosecond response time with improved minimum supply voltage capability, and a maximum output power of $10\,\mathrm{W}$ . For an output voltage of $850\,\mathrm{m}\mathrm{V}$ , the feedforward control reduces the required voltage overhead by $60\,\mathrm{m}\mathrm{V}$ for a transient load step from $10\%$ to $100\%$ of the nominal load. This can reduce the overall power consumption of the microprocessor by $7\%$ .
TL;DR: A novel low-inductance packaging structure for a wire-bond-based multichip phase-leg SiC MOSFET module to suppress the voltage overshoot is proposed, based on the adjacent decoupling concept achieved by several decoupled capacitors to reduce the size of the commutation loop.
Abstract: The silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has a more serious voltage overshoot than the silicon insulated gate bipolar transistor (IGBT) due to the fundamental differences of the devices’ parasitic parameters. In this paper, a novel low-inductance packaging structure for a wire-bond-based multichip phase-leg SiC MOSFET module to suppress the voltage overshoot is proposed. This packaging structure is based on the adjacent decoupling concept achieved by several decoupling capacitors to reduce the size of the commutation loop. The improvement in the packaging parasitics has been verified through an Ansys Q3D extractor. Furthermore, the influence of adjacent decoupling capacitors is analyzed in detail by frequency-domain analysis and verified with LTspice simulation analysis. Thereafter, the selection and thermal reliability of adjacent decoupling capacitors are expounded. The experimental results demonstrate the effectiveness and superiority of the proposed packaging structure.
TL;DR: In this paper, a new method for measuring capacitor voltages in multilevel flying capacitor (FC) converters that requires only one voltage sensor per phase leg is proposed, which is subsequently used to balance the capacitor voltage using only the measured ac voltage.
Abstract: This paper proposes a new method for measuring capacitor voltages in multilevel flying capacitor (FC) converters that requires only one voltage sensor per phase leg. Multiple dc voltage sensors traditionally used to measure the capacitor voltages are replaced with a single voltage sensor at the ac side of the phase leg. The proposed method is subsequently used to balance the capacitor voltages using only the measured ac voltage. The operation of the proposed measurement and balancing method is independent of the number of the converter levels. Experimental results presented for a five-level FC converter verify effective operation of the proposed method.
TL;DR: This paper proposes a novel diode-clamped modular multilevel converter with simplified capacitor voltage-balancing control, using low-power rating diodes to clamp the capacitor voltages of the converter.
Abstract: Multilevel converters have become very attractive for high-voltage-level power conversion in renewable power generation applications. The converter topology is an important issue in the studies of multilevel converter. Many multilevel topologies have been developed, but few of them are qualified with capacitor voltage self-balancing capability. This paper proposes a novel diode-clamped modular multilevel converter with simplified capacitor voltage-balancing control. In this topology, low-power rating diodes are used to clamp the capacitor voltages of the converter. Only the top submodule in each arm of the converter requires capacitor voltage control. Consequently, very few voltage sensors are needed for voltage control and the control computation burden is reduced greatly when the quantity of the submodules is high. A simple voltage-balancing control method with carrier phase-shifted modulation strategy is developed for this topology. Experiments based on a laboratory prototype were carried out and the results validated the capacitor-balancing performance of the proposed topology.
TL;DR: In this paper, a dc-split capacitor circuit with equal capacitances was proposed and tested experimentally in a single-phase converter for diverting second harmonic ripple away from its dc source or load.
Abstract: Instead of bulky electrolytic capacitors, active power decoupling circuit can be introduced to a single-phase converter for diverting second harmonic ripple away from its dc source or load. One possible circuit consists of a half-bridge and two capacitors in series for forming a dc-split capacitor, instead of the usual single dc-link capacitor bank. Methods for regulating this power decoupler have earlier been developed, but almost always with equal capacitances assumed for forming the dc-split capacitor, even though it is not realistic in practice. The assumption should, hence, be evaluated more thoroughly, especially when it is shown in the paper that even a slight mismatch can render the power decoupling scheme ineffective and the IEEE 1547 standard to be breached. A more robust compensation scheme is, thus, needed for the dc-split capacitor circuit, as proposed and tested experimentally in the paper.
23 Apr 2017
TL;DR: A data-driven experimental analysis on capacitor bank switching event at a distribution grid in Riverside, CA using data from two distribution level phasor measurement units, a.k.a, μPMUs is conducted, taking a first step in using μPMU data to conducting a detailed analysis of how different voltage-levels are affected by capacitorBank switching events in distribution systems.
Abstract: In this paper, we conduct a data-driven experimental analysis on capacitor bank switching event at a distribution grid in Riverside, CA using data from two distribution level phasor measurement units, a.k.a, μPMUs. Of particular interest was to detect the capacitor bank switching events based on feeder-level and load-level μPMUs and thus eliminating the need to install separate sensors for the switched capacitor banks. In addition, the operational parameters of capacitor bank is investigated. Moreover, the dynamic effects of capacitor bank switching events is also considered through voltage and current synchrophasor data. This paper takes a first step in using μPMU data to conducting a detailed analysis of how different voltage-levels are affected by capacitor bank switching events in distribution systems.
TL;DR: A novel DHB power-decoupling control scheme without current sensor is proposed for single-phase inverters and has the advantage of current-sensorless configuration especially when it needs information from inverter phase-lock-loop (PLL).
Abstract: In this paper, a novel DHB power-decoupling control scheme without current sensor is proposed for single-phase inverters. As electrolyte capacitors are conventionally used; however, these capacitors limit ripple current capability and circuit reliability. Film capacitors improve the ripple current capability, size reduction, and circuit reliability. Conventionally, non-isolated topologies are used for power decoupling. The volume of the decoupling capacitor per unit energy in isolated bidirectional power decoupling topologies is reduced as compared to nonisolated due to unrestricted voltage across the decoupling capacitor. Voltage-fed Phase-Shift Dual Half-Bridge (DHB) is preferred with film capacitors as it has the least number of components in isolated bidirectional topologies. However, in DHB, power decoupling controller is a challenge as current control is conventionally required. The challenge has been overcome with novel current-sensorless dc link ripple rejection control. The controller has the advantage of current-sensorless configuration especially when it needs information from inverter phase-lock-loop (PLL). The proposed power decoupling control scheme is independent of the inverter control and universal. A new dynamic analysis has been carried out by taking into account the input-voltage dynamics. The advantage of the DHB is that it has single pole behavior and, hence, sufficient bandwidth can be obtained. Simulations and experiments have been performed to verify the analysis of the power decoupling control scheme and the capability of film-capacitor DHB for power decoupling.
TL;DR: A reference error calibration scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) verified with two prototypes and achieves at least 9-dB improvement on signal-to-(Noise + Distortion) ratio (SNDR) ratio after calibration.
Abstract: This paper presents a reference error calibration scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a reference error often occurs in high-speed SAR ADCs due to the signal dependent fast switching transient, and leads to a large differential nonlinearity and missing codes, eventually degrading conversion accuracy. The calibration concept aims to differentiate the error outputs and correct them by simply performing a subtraction in the digital domain. It runs in the background with a little hardware overhead, and does not depend on the type of the input signal or reduce the dynamic range. Two prototypes were measured which are made up of different reference generation circuits. Design #1 has the reference voltage from off-chip and a 3-pF decoupling capacitor on-chip, while design #2 includes an on-chip reference buffer. Both designs were fabricated in 65-nm CMOS and achieve at least 9-dB improvement on signal-to-(Noise + Distortion) ratio (SNDR) after calibration. The total core area is around 0.012 mm2 for both chips and the Nyquist SNDR of designs #1 and #2 is 59.03 and 57.93 dB, respectively.
TL;DR: In this paper, the authors extended an existing switched-capacitor state space modeling framework to include the bottom plate capacitor, which is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter.
Abstract: The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves $86\%$ maximum efficiency at $4.6\,\text{W}/\text{m}\text{m}^2$ power density while converting from a 1.8 V input voltage to 830 mV output voltage.
01 Mar 2017
TL;DR: In this paper, a novel control strategy is proposed by the means of harmonic injections in the conjunction with gain control to eliminate completely both the line frequency and the second-order harmonic of the capacitor voltage ripple.
Abstract: The modular multi-level converter (MMC) is the most prominent interface converter used between the HVDC grid and the HVAC grid One of the important design challenges in MMC is to reduce the capacitor size In the current practice, a rather large capacitor bank is required to store line-frequency related circulating energy, even though a number of control strategies have been introduced to reduce the capacitor voltage ripples In the present paper, a novel control strategy is proposed by the means of harmonic injections in the conjunction with gain control to eliminate completely both the line frequency and the second-order harmonic of the capacitor voltage ripple Ideally, the proposed method works with the full bridge topology However, the concept also works with half bridge topology with significant reduction of line frequency related ripple To gain a better understanding of nature of circulating energy and means of reducing it, the method of state plane analysis is employed to offer visual support In addition, the design trade-off between full bridge MMC and half bridge MMC is presented and a novel control strategy for hybrid MMC is proposed Finally, the work is supported with a scale down hardware demonstration
TL;DR: This paper proposes a hardware reconfiguration technique based on only two fuses and one thyristor per leg that allows a safe postfault operation recovery of the 3L-NPC converter and proposes a mathematical design of the filter needed to connect these two different topologies.
Abstract: This paper deals with a hybrid fault-tolerant converter topology. It is performed through the connection of a classical three-phase three-level neutral-point-clamped (3L-NPC) converter with a fourth three-level flying capacitor (3L-FC) leg. The 3L-FC leg actively balances the 3L-NPC neutral-point voltage. For normal operation mode, this paper proposes a mathematical design of the filter needed to connect these two different topologies. Experimentally, and thanks to the already existing decoupling capacitors of the 3L-NPC converter, this filter requires the addition of only one low size inductance. When one fault of the power switch of the 3L-NPC occurs, this paper proposes a hardware reconfiguration technique based on only two fuses and one thyristor per leg allows a safe postfault operation recovery. This is achieved thanks to a simple fault-detection method and a new technique that combines fault leg isolation and corresponding phase postfault connection to the neutral point. Also, a dedicated field-programmable gate array (FPGA)-based control of the reconfigured converter is synthetized to ensure power system availability under fault operation mode. The converter fault-tolerant capabilities are addressed through simulation results and original overall experimental validations of the fault detection and isolation and the postfault operation steps, carried out on a 15-kW prototype converter.
TL;DR: In this paper, a dc-link shunt compensator (DSC) was proposed to improve the performance of a single-phase diode rectifier with small DC-link capacitors.
Abstract: The single-phase diode rectifier system with small dc-link capacitor shows wide diode conduction time and it improves the grid current harmonics. By shaping the output power, the system meets the grid current harmonics regulation without any power factor corrector or grid filter inductor. However, the system has torque ripple and suffers efficiency degradation due to the insufficient dc-link voltage. To solve this problem, this paper proposes the dc-link shunt compensator (DSC) for small dc-link capacitor systems. DSC is located on dc-node in parallel and operates as voltage source, improving the system performances. This circuit helps the grid current-shaping control during grid-connection time, and reduces the flux-weakening current by supplying the energy to the motor during grid-disconnection time. This paper presents a power control method and the design guideline of DSC. The feasibility of DSC is verified by simulation and experimental results.
TL;DR: In this article, a new three-level neutral-point-clamped quasi-Z-source inverter topology is proposed to reduce the Z-source network capacitance voltage stress and inhibit the start inrush current.
Abstract: A new three-level neutral-point-clamped quasi-Z-source inverter topology is proposed. The topology can effectively reduce the Z-source network capacitor voltage stress and inhibit the start inrush current, thus low-voltage capacitors can be selected to reduce the volume and cost of the inverter. In addition, the changed structure will not affect the boost ability and all existing modulation methods can be used directly. The proposed topology is validated by simulations.
TL;DR: The virtual infinite capacitor (VIC) is defined as a nonlinear capacitor that has the property that for an interval of the charge Q (the operating range), the voltage V remains constant.
Abstract: We define the virtual infinite capacitor (VIC) as a nonlinear capacitor that has the property that for an interval of the charge Q (the operating range), the voltage V remains constant. We propose a lossless approximate realisation for the VIC as a simple circuit with two controllers: a voltage controller acts fast to maintain the desired terminal voltage, while a charge controller acts more slowly and maintains the charge Q in the desired operating range by influencing the incoming current. The VIC is useful as a filter capacitor for various applications, for example, power factor compensators (PFC), as we describe. In spite of using small capacitors, the VIC can replace a very large capacitor in applications that do not require substantial energy storage. We give simulation results for a PFC working in critical conduction mode with a VIC for output voltage filtering.
TL;DR: In this article, a solid state variable capacitor (SSVC) with minimum capacitance is proposed to absorb the ripple power pulsating at twice the line frequency (2 ω ripple power).
Abstract: A solid state variable capacitor (SSVC) with minimum capacitor is proposed. A variable ac capacitor (with capacitance varied from 0 to $C_{{{\rm ac}}}$ ) is traditionally implemented by an H-bridge inverter and a large electrolytic dc capacitor, whose capacitance is 20 times of the ac capacitor's value, in order to absorb the ripple power pulsating at twice the line frequency (2 ω ripple power). The proposed SSVC system consists of an H-bridge and an additional phase leg connected to an ac capacitor with fixed capacitance $C_{{{\rm ac}}}$ and can reduce the dc capacitance to minimum value for absorbing switching ripples. The ac capacitor absorbs the 2 ω component and theoretically can eliminate 2 ω ripples to the dc capacitor completely. The total capacitor size is reduced by 13 times if same type capacitors (film) are used. Moreover, the proposed SSVC shows special advantages in terms of the switches’ current and voltage stress compared to other applications and the total device power rating is only 1.125 times of H-bridge. Since the proposed SSVC only has a small dc capacitor, a novel control system directly based on ripple power is also proposed to achieve stable dc voltage and fast dynamic response. Simulation and experimental results are shown to prove the effectiveness of the proposed SSVC with minimum capacitor.
01 Jun 2017
TL;DR: A review of IMMD technologies is given and current research and future prospects are studied and optimum selection of DC link capacitor is achieved based on the electrical, thermal and economical model.
Abstract: In this paper, selection of optimum DC link capacitor for Integrated Modular Motor Drives (IMMD) is presented. First, a review of IMMD technologies is given and current research and future prospects are studied. Inverter topologies and gate drive techniques are evaluated in terms of DC link performance. The urge for volume reduction in IMMD poses a challenge for the selection of optimum DC link capacitor. DC Link capacitor types are discussed and critical aspects in selecting the DC links capacitor are listed. Analytical modeling of DC link capacitor parameters is performed and it is verified by simulations conducted using MATLAB/Simulink. Optimum selection of DC link capacitor is achieved based on the electrical, thermal and economical model.
TL;DR: This brief presents a 40-nW 0.5-V supply voltage and 0.24-V output reference for an energy harvester using a resistorless proportional-to-absolute-temperature circuit and the low-voltage high-power-supply-rejection-ratio current source to improve the accuracy and line regulation performance of the reference.
Abstract: This brief presents a 40-nW 0.5-V supply voltage and 0.24-V output reference for an energy harvester. The emitter–base voltage of a PNP transistor is divided by the presented switch capacitor circuit to obtain the low output reference. The resistorless proportional-to-absolute-temperature circuit and the low-voltage high-power-supply-rejection-ratio current source are used to improve the accuracy and line regulation performance of the reference. The proposed bandgap reference is implemented in a 0.18- $\mu\text{m}$ standard complementary metal–oxide–semiconductor process and has a total area of 0.058 mm2. Test results show that the minimum supply voltage is 0.5 V due to the clock bootstrap and $2\times\text{VDD}$ doubler. The line regulation is about 1.1 mV/V in the supply voltage range of 0.5–0.9 V. With 3-bit trimming, the temperature coefficient of 58 ppm/°C in the range of −25 °C–85 °C and the accuracy of 0.9% $(3\delta)$ can be achieved.
TL;DR: In this article, the transient response of negative capacitance (NC) in an organic ferroelectric capacitor is experimentally investigated, where the external series resistor is altered as a tuning parameter to explore the impact of the RC time constant on the NC time duration.
Abstract: The transient response of negative capacitance (NC) in an organic ferroelectric capacitor is experimentally investigated. To observe the transient response of the NC, a simple series network, consisting of an external series resistor and an organic ferroelectric capacitor, is built. The Landau coefficients of the organic ferroelectric capacitor were extracted from the measured polarization versus applied electric field data. A circuit level simulation was provided with the extracted parameters based on the Landau–Khalatnikov equation. To explore the impact of the RC time constant on the NC time duration in the RC series circuit, the external series resistor is altered as a tuning parameter. Also, the effect of various temperatures of the ferroelectric capacitor on the NC time duration is experimented. This paper demonstrates that either the external resistor or the ambient temperature can change the NC time duration in an organic ferroelectric capacitor.
TL;DR: This paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied.
Abstract: Capacitor sizing is a crucial step when designing charge-scaling digital-to-analog converters (DACs). Larger capacitor size can achieve better circuit accuracy and performance due to less impact from process gradient, parasitic mismatch, and local variation. However, it also results in larger chip area and higher power consumption. The size of binary-weighted capacitors in charge-scaling DACs is highly sensitive to the routing parasitics. Unmatched routing parasitics among binary-weighted capacitors will lead to large capacitor size for satisfying circuit accuracy and performance. Previous work focuses on the study of generating high-quality common-centroid placement of unit capacitor arrays while ignoring routing parasitics. None of them address the sizing of binary-weighed capacitors. This paper presents the first problem formulation in the literature which simultaneously considers capacitor sizing and parasitic matching during common-centroid capacitor layout generation such that the power consumption is minimized while the circuit accuracy/performance is also satisfied. Experimental results show that the proposed approach can achieve very significant chip area and power reductions compared with the state-of-the-art approaches.