Showing papers on "Digital electronics published in 2019"

All-printed large-scale integrated circuits based on organic electrochemical transistors.

Abstract: The communication outposts of the emerging Internet of Things are embodied by ordinary items, which desirably include all-printed flexible sensors, actuators, displays and akin organic electronic interface devices in combination with silicon-based digital signal processing and communication technologies. However, hybrid integration of smart electronic labels is partly hampered due to a lack of technology that (de)multiplex signals between silicon chips and printed electronic devices. Here, we report all-printed 4-to-7 decoders and seven-bit shift registers, including over 100 organic electrochemical transistors each, thus minimizing the number of terminals required to drive monolithically integrated all-printed electrochromic displays. These relatively advanced circuits are enabled by a reduction of the transistor footprint, an effort which includes several further developments of materials and screen printing processes. Our findings demonstrate that digital circuits based on organic electrochemical transistors (OECTs) provide a unique bridge between all-printed organic electronics (OEs) and low-cost silicon chip technology for Internet of Things applications. Though designing digital circuits using organic electrochemical transistors (OECTs) is promising due to their high performance, inherent large footprint limits adoption. Here, the authors report staggered top-gate OECTs for all-printed integrated circuits with fast switching and small footprint.

p-bits for probabilistic spin logic

Abstract: We introduce the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing. We show that low barrier magnets or LBMs provide a natural physical representation for p-bits and can be built either from perpendicular magnets designed to be close to the in-plane transition or from circular in-plane magnets. Magnetic tunnel junctions (MTJs) built using LBMs as free layers can be combined with standard NMOS transistors to provide three-terminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ device used in embedded magnetic random access memory technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that the concept of p-bits and p-circuits will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ; any fluctuating resistor could be combined with a transistor to implement it, while completely digital implementations using conventional CMOS technology are also possible. The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely, stochastic machine learning and quantum computing. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man's q-bit. Initial demonstrations based on full SPICE simulations show that several optimization problems, including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology.

ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress

Abstract: The IARPA SuperTools program requires the development of superconducting electronic design automation (S-EDA) and superconducting technology computer-aided design (S-TCAD) tools aimed at enabling the reliable design of complex superconducting digital circuits with millions of Josephson junctions. Within the SuperTools program, the ColdFlux project addresses S-EDA and S-TCAD tool research and development in four areas: 1) RTL synthesis, architectures and verification; 2) analog design and layout synthesis; 3) physical design and test; and 4) device and process modeling/simulation and cell library design. Capabilities include, but are not limited to, the following: device level modeling and simulation of Josephson junctions, modeling and simulation of the superconducting process manufacturing processes, powerful new electrical circuit simulation, parameterized schematic and layout libraries, optimization, compact SPICE-like model extraction, timing analysis, behavioral, register-transfer-level and logic syntheses, clock tree synthesis, placement and routing, layout-versus-schematic extraction, functional verification, and the evaluation of designs in the presence of magnetic fields and trapped flux. ColdFlux consists of six research groups from four continents. Here, we present an overview of the current and planned activities related to the project and justify the design assumptions and decisions that were made to allow the development of design tools for million-gate circuits.

A Novel Adder Circuit Design in Quantum-Dot Cellular Automata Technology

Abstract: Quantum-dot Cell Automata (QCA) technology is a promising alternative technology for CMOS technology. In this technology, the ultra-dense and low-latency digital circuits are designed. One of the important digital circuits is Full Adder (FA). In this paper, a new and efficient multilayer QCA full adder circuit is designed and evaluated. In the designed full adder circuit, sum and carry output are designed in separated layers. Then, a novel and efficient 4-bit Ripple Carry Adder (RCA) circuit is designed based on this new FA circuit. The proposed QCA circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the proposed 4-bit QCA RCA requires 135 QCA cells, 0.06 μm2 area and 5 clock phases. The comparison shows that the proposed QCA circuits have advantages compared to other QCA circuits in terms of area, latency, and cost.

Ultra-Low Power Silicon Neuron Circuit for Extreme-Edge Neuromorphic Intelligence

Abstract: Recent years have seen an increasing interest in the development of artificial intelligence circuits and systems for cloud-less edge computing applications. In an effort to reduce power consumption even further, we propose beyond von-Neumann in-memory computing architectures that can process the signals at the sensor side using ultra-low power mixed-signal analog/digital circuits which have properly matched dynamics and time-constants. In this paper, we propose one of the main computing elements of such architectures, namely the silicon neuron, designed using analog circuits in an advanced FDSOI 22 nm node. Here we optimize the design of an Adaptive Exponential Integrate and Fire (AdExp IF) neuron model for producing neural dynamics with biologically plausible time constants. We explore the options of the 22 nm FDSOI technology to address the analog design issues that arise from advanced scaling (such as leakage) and minimize power consumption by using a novel current comparator circuit with current-driven positive feedback. We present circuit simulation results which reproduce biologically plausible responses and compare the circuit energy per spike with state-of-the-art architectures. The proposed neuron design consumes one order of magnitude less power compared to the state-of-the-art and two orders of magnitude less compared to a pure digital implementation.

Soft Robots for Extreme Environments: Removing Electronic Control

Abstract: The ignition of flammable liquids and gases in offshore oil and gas environments is a major risk and can cause loss of life, serious injury, and significant damage to infrastructure. Power supplies that are used to provide regulated voltages to drive motors, relays, and power electronic controls can produce heat and cause sparks. As a result, the European Union requires ATEX certification on electrical equipment to ensure safety in such extreme environments. Implementing designs that meet this standard is time-consuming and adds to the cost of operations. Soft robots are often made with soft materials and can be actuated pneumatically, without electronics, making these systems inherently compliant with this directive. In this paper, we aim to increase the capability of new soft robotic systems moving from a one-to-one control-actuator architecture and implementing an electronics-free control system. We have developed a robot that demonstrates locomotion and gripping using three-pneumatic lines: a vacuum power line, a control input, and a clock line. We have followed the design principles of digital electronics and demonstrated an integrated fluidic circuit with eleven, fully integrated fluidic switches and six actuators. We have realized the basic building blocks of logical operation into combinational logic and memory using our fluidic switches to create a two-state automata machine. This system expands on the state of the art increasing the complexity over existing soft systems with integrated control.

A Design Methodology and Device/Circuit/Architecture Compatible Simulation Framework for Low-Power Magnetic Quantum Cellular Automata Systems

Abstract: CMOS device scaling is facing a daunting challenge with increased parameter variations and exponentially higher leakage current every new technology generation. Thus, researchers have started looking at alternative technologies. Magnetic Quantum Cellular Automata (MQCA) is such an alternative with switching energy close to thermal limits and scalability down to 5nm. In this paper, we present a circuit/architecture design methodology using MQCA. Novel clocking techniques and strategies are developed to improve computation robustness of MQCA systems. We also developed an integrated device/circuit/system compatible simulation framework to evaluate the functionality and the architecture of an MQCA based system and conducted a feasibility/comparison study to determine the effectiveness of MQCAs in digital electronics. Simulation results of an 8-bit MQCA-based Discrete Cosine Transform (DCT) with novel clocking and architecture show up to 290X and 46X improvement (at iso-delay and optimistic assumption) over 45nm CMOS in energy consumption and area, respectively.

Optimization of the area efficiency and robustness of a QCA-based reversible full adder

Abstract: Recently, quantum dot cellular automata (QCAs) have evolved as the most promising candidate to overcome the fundamental nanoscale limitations of present complementary metal–oxide–semiconductor (CMOS) technology. Owing to their quasiadiabatic switching, QCAs have huge potential for the design of THz-frequency logic circuits and ultralow-power digital circuits with extremely high device density. The aim of the work presented herein is to maximize the benefits of a QCA-based circuit design by deploying reversible computing logic. A highly efficient reversible QCA-based full adder is proposed by using a three-input and five-input majority gate architecture. The proposed design demonstrates significant improvements in circuit complexity, area efficiency, and quantum cost while retaining performance in terms of latency and area usage. Coplanar crossovers are properly realized using 180° clock zones. The performance of the proposed design surpasses that of recent literature designs, with a 25% reduction in the circuit complexity, a 28% saving in the total area, a 24.57% decrease in the cell area, and an approximately 1/4 reduction in the quantum cost. To verify the feasibility of the proposed design, its thermal robustness is analyzed and hazard analysis is also performed. The proposed full adder is further employed to realize reversible ripple-carry adders (RCAs) of variable size. The proposed RCAs also show significant improvements in terms of the mentioned performance parameters.

Design of Novel Coplanar Counter Circuit in Quantum Dot Cellular Automata Technology

Abstract: One of the emerging technology that can be used for replacing CMOS technology is Quantum-dot Cellular Automata (QCA) technology. Counter circuits are widely used circuits in the design of digital circuits. This paper presents and evaluates circuits for 2-, 3-, 4-, and 5-bit coplanar counter in the QCA technology. The designed QCA coplanar counter circuits are based on the modified D-Flip-Flop (D-FF) circuit that is designed in this paper. The designed QCA circuits are implemented and verified by using QCADesigner tool version 2.0.3. The results show that the designed circuits for 2-, 3-, 4-, and 5-bit coplanar counter contain 44 (0.03 μm2), 93 (0.07 μm2), 160 (0.13 μm2), and 245 (0.2 μm2) quantum cells (area). The comparison results indicate that the designed circuits have advantages compared to other QCA circuits in terms of cost, area, and cell count.

Design of efficient coplanar 1-bit comparator circuit in QCA technology

Abstract: QCA technology is an emerging and promising technology for implementation of digital circuits in nano-scale. The comparator circuits play an important role in digital circuits. In this work, a new and efficient coplanar 1-bit comparator circuit is proposed and evaluated in the QCA technology. The designed coplanar 1-bit QCA comparator circuit is constructed based on majority gate, XNOR gate and inverter gate that are designed carefully. The functionality of the designed coplanar 1-bit QCA comparator circuit is verified by using QCADesigner version 2.0.3. The obtained results indicate that the designed 1-bit QCA comparator circuit requires 0.03 µm 2 area and 38 QCA cells. It also has 0.5 clock cycles delay. The comparison demonstrates that the designed QCA comparator circuit provides improvements in comparison with other QCA comparator circuits in terms of effective area, cell count, and delay as well as cost.

Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits

Abstract: A framework is proposed for activity-dependent timing degradation due to p-FET negative bias temperature instability (NBTI) in digital circuits. A fixed-time compact model is proposed for NBTI and validated with physical model predictions for various digital circuits under different input signal slew and fan-out load conditions. The model is used to predict the timing degradation in digital circuits under arbitrary input activities. An equivalent degradation level is found that can be applied to all p-FETs in the circuit and can serve as an upper bound of degradation due to arbitrary input activity and avoid the conservative worst case dc analysis. The activity dependence is studied in microprocessors as well as arithmetic circuits under different actual workloads.

Analytical modeling for static and dynamic response of organic pseudo all-p inverter circuits

Abstract: This paper presents the performance analysis of an all-p-organic pseudo-inverter circuit using dual gate organic thin film transistors. The proposed inverter design has shown significantly high performance in terms of noise margin, gain and propagation delay, leading to the design of more robust digital circuits that, too, exhibit augmented performance. The parameters of the all-p-organic pseudo-inverter are compared with those of zero-Vgs load logic (ZVLL) and dynamic load logic based conventional inverters, and a substantial improvement is found for the novel combination of a dual gate flexible TFT with a pseudo-design. Performance parameters were deeply analyzed, and we observed that the noise margin is improved by 42.8% as compared to ZVLL based conventional inverters. A bootstrap technique was implemented to further improve the performance and reduce the threshold voltage drop. The performance parameters were analyzed mathematically and compared with simulated values. The static as well as dynamic characteristics of organic pseudo-all-p inverter, with and without bootstrap technique, were observed. Static power consumption of the organic pseudo-all-p inverter was estimated. In this way, improvement of noise margin by the bootstrap circuit of the organic pseudo-inverter is characterized. The reduced threshold voltage applied to design of low power circuits enables longer power backup for various applications.

CMOS Inverter as Analog Circuit: An Overview

Abstract: Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

Chaos-Based Physical Unclonable Functions

Abstract: The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

Low-latency adiabatic superconductor logic using delay-line clocking

Abstract: Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.

Particle computation: complexity, algorithms, and logic

Abstract: We investigate algorithmic control of a large swarm of mobile particles (such as robots, sensors, or building material) that move in a 2D workspace using a global input signal (such as gravity or a magnetic field). Upon activation of the field, each particle moves maximally in the same direction until forward progress is blocked by a stationary obstacle or another stationary particle. In an open workspace, this system model is of limited use because it has only two controllable degrees of freedom—all particles receive the same inputs and move uniformly. We show that adding a maze of obstacles to the environment can make the system drastically more complex but also more useful. We provide a wide range of results for a wide range of questions. These can be subdivided into external algorithmic problems, in which particle configurations serve as input for computations that are performed elsewhere, and internal logic problems, in which the particle configurations themselves are used for carrying out computations. For external algorithms, we give both negative and positive results. If we are given a set of stationary obstacles, we prove that it is NP-hard to decide whether a given initial configuration of unit-sized particles can be transformed into a desired target configuration. Moreover, we show that finding a control sequence of minimum length is PSPACE-complete. We also work on the inverse problem, providing constructive algorithms to design workspaces that efficiently implement arbitrary permutations between different configurations. For internal logic, we investigate how arbitrary computations can be implemented. We demonstrate how to encode dual-rail logic to build a universal logic gate that concurrently evaluates and, nand, nor, and or operations. Using many of these gates and appropriate interconnects, we can evaluate any logical expression. However, we establish that simulating the full range of complex interactions present in arbitrary digital circuits encounters a fundamental difficulty: a fan-out gate cannot be generated. We resolve this missing component with the help of 2 × 1 particles, which can create fan-out gates that produce multiple copies of the inputs. Using these gates we provide rules for replicating arbitrary digital circuits.

A 1.5–1.9-GHz All-Digital Tri-Phasing Transmitter With an Integrated Multilevel Class-D Power Amplifier Achieving 100-MHz RF Bandwidth

Abstract: We present a prototype RF transmitter with an integrated multilevel class-D power amplifier (PA), implemented in 28-nm CMOS. The transmitter utilizes tri-phasing modulation, which combines three constant-envelope phase-modulated signals with coarse amplitude modulation in the PA. This new architecture achieves the back-off efficiency of multilevel outphasing, without linearity-degrading discontinuities in the RF output waveform. Because all signal processing is performed in the time domain up to the PA, the entire system is implemented with digital circuits and structures, thus also enabling the use of synthesis and place-and-route CAD tools for the RF front end. The effectiveness of the digital tri-phasing concept is supported by extensive measurement results. Improved wideband performance is validated through the transmission of orthogonal frequency-division multiplexing (OFDM) bandwidths up to 100 MHz. Enhanced reconfigurability is demonstrated with non-contiguous carrier aggregation and digital carrier generation between 1.5 and 1.9 GHz without a frequency synthesizer. For a 20-MHz 256-QAM OFDM signal at 3.5% error vector magnitude (EVM), the transmitter achieves 22.6-dBm output power and 14.6% PA efficiency. Thanks to the high linearity enabled by tri-phasing, no digital predistortion is needed for the PA.

New modified-majority voter-based efficient QCA digital logic design

Abstract: Quantum-dot cellular automata (QCA) is an emerging nanotechnology and a possible alternative solution to the limitation of complementary metal oxide semiconductor (CMOS) technology. One of the most attractive fields in QCA is the implementation of configurable digital systems. This article presents a novel multifunctional gate called the modified-majority voter (MMV). The proposed gate works on the explicit interaction of the cell characteristic property for the implementation of digital circuits. This prominent feature of the proposed gate reduces the maximum hardware cost and implements highly efficient QCA structures. To verify the functionality of the proposed gate, some physical proofs, truth table and computational simulation results are performed. These results assured the validity of the existence of the proposed gate. It also dissipates less energy which has been calculated under three separate tunnelling energy levels using the QCAPro tool. To prove the effectiveness of the proposed MMV ...

Efficient designs of reversible latches with low quantum cost

Abstract: Reversible computing is one of the most promising technologies in the design of low-power digital circuits, optical information processing, quantum computing, DNA computing, digital signal processing, and nanotechnology. The main purpose of the design of reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. A gate/block is reversible if the number of inputs and the number of outputs are equal and there is one-to-one correspondence between them. Latches are considered as one of the most important digital structures that are widely used as building blocks in the design of sequential circuits. Here, eight new reversible blocks are first offered. Then using some of them, several effective designs of reversible D, T, and J-K latches are proposed. The results of the evaluations indicate that the proposed latches are superior in terms of quantum cost (QC) than previous designs. Moreover, they are very close to or better than the best previous designs in terms of criteria such as gate count (GC), constant inputs (CI), and garbage outputs (GO).

Effective Logic Synthesis for Threshold Logic Circuit Design

Abstract: This paper presents a novel and effective logic synthesis flow able to identify threshold logic functions during the technology mapping process. It provides more efficient logic covering, exploring also redundant cuts. Moreover, the proposed design flow takes into account different circuit area estimations, such as the sum of input weights and threshold values, the gate fanin and the number of threshold logic gates. As a result, the mapped circuits present a reduction up to 47% and 67% in area and logic depth, respectively, in comparison to the most recent related approaches.

Automated Search-Based Functional Approximation for Digital Circuits

Abstract: The problem of developing an approximate implementation of a given combinational circuit can be formulated as a multi-objective design problem and solved by means of a search algorithm. This approach usually provides many solutions showing high-quality tradeoffs between key design objectives; however, it is very computationally expensive. This chapter presents a general-purpose method based on genetic programming for an automated functional approximation of combinational circuits at the gate and register-transfer levels. It surveys relevant error metrics and circuit parameters that are typically optimized by genetic programming. A special attention is given to the techniques capable of providing formal guarantees in terms of error bounds and accelerating the search process. Case studies dealing with approximate implementations of arithmetic circuits and image operators are presented to highlight the quality of results obtained by the search-based functional approximation in completely different application domains.

Short-Circuit Fault Diagnosis Based on Rough Sets Theory for a Single-Phase Inverter

Abstract: The short-circuit (SC) fault diagnosis in inverters is an important procedure for the continuity of the performance and the extension of its useful life. The methods of diagnosis of SC failures produce good results, however, they present unfavorable aspects: they detect only one of the faults of SC, that is to say, the hard switch fault (HSF) or the fault under load (FUL); depend on switch parameters; and use artificial intelligence (AI) techniques in their algorithms, which are executed simultaneously with the inverter operation. This article presents a method of diagnosing SC faults performed with a digital circuit. The proposed method identifies short-circuit faults: HSF and FUL; can be used with any switch, regardless of its parameters; and does not use AI algorithms and techniques concurrently with inverter operation. The digital diagnostic circuit is obtained with the use of rough sets theory (RST), which optimizes and defines a minimum set of variables necessary to diagnose faults. Applying RST to the variables obtains a set of diagnostic rules. These rules are performed with basic logic functions and, for this reason, a digital diagnostic circuit is obtained. The diagnostic variables are the command signals and the voltage source inverter switches currents. The simulation and experimental results validate the shown diagnostic method.

Effective Designs of Reversible Vedic Multiplier

Abstract: Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

A New Method for Design of CNFET-Based Quaternary Circuits

Abstract: In this paper, a new method for designing quaternary circuits in carbon nanotube field-effect transistor (CNFET) technology is proposed. Beyond many advantages of multi-valued logics (MVLs), the conversion of bits of a byte between quaternary and binary logic is easy and can be done independently. Therefore, this logic can be used effectively for wholly quaternary circuit design or beside binary logic as part of a great digital system. Thanks to particular capabilities of CNFET technology, proposed designs are implemented in this technology. These complementary symmetric gates are merely made by transistors and require only one supply voltage in addition to ground level. The proposed design for implementing standard quaternary inverter (SQI) generates three inherently binary inverters in quaternary logic as well: positive quaternary inverter (PQI), negative quaternary inverter (NQI) and symmetric quaternary inverter (SyQI). Based on the proposed design, new quaternary NAND (QNAND) and quaternary NOR (QNOR) gates are presented as well. These gates could be used as fundamental blocks for implementing complex digital circuits. QNAND and QNOR may be designed to adopt up to four inputs; however, in general applications, designs with two inputs are used. Proposed gates are simulated by means of Synopsys HSPICE tool with the standard 32 nm CNFET Stanford model, and performance parameters including maximum delay time, average power and energy consumption are extracted and compared with the simulation results of the state-of-the-art designs. The results indicate priority of proposed designs such that the delay time and energy consumption are roughly equal or less than half and one-third of other presented designs, respectively. Moreover, the voltage transfer curve (VTC) of proposed gates demonstrates the proper noise margin values from 90 mV up to 113 mV for different gates. For evaluating stability and robustness of these gates, more simulations are carried out by considering process deviations in which the proposed designs demonstrate proper performance among all in the most simulations.

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

Abstract: This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and red...

Survey of Stochastic-Based Computation Paradigms

Abstract: Effectively tackling the upcoming “zettabytes” data explosion requires a huge quantum leap in our computing power and energy efficiency. However, with the Moore’s law dwindling quickly, the physical limits of CMOS technology make it almost intractable to achieve high energy efficiency if the traditional “deterministic and precise” computing model still dominates. Worse yet, the upcoming data explosion mostly comprises statistics gleaned from uncertain, imperfect real-world environment. As such, the traditional computing means of first principles modeling or explicit statistical modeling will very likely be ineffective to achieve flexibility, autonomy, and human interaction. The bottom line is clear: given where we are headed, the fundamental principle of modern computing—deterministic logic circuits can flawlessly emulate propositional logic deduction governed by Boolean algebra—has to be reexamined, and transformative changes in the foundation of modern computing must be made. This paper surveys some of the most important works on stochastic-based computing. We specifically focus on four important research areas: 1) random number generation, 2) stochastic computing, 3) stochastic electronics, and 4) emerging device technology and its potential application in stochastic computing. All these research works share two distinctive features. First, they embrace and exploit quantum-induced randomness as an invaluable information carrier, not the “villain of correct computation” to be suppressed. Second, the theoretical foundation underpinning most of these works are based on neither the Boolean algebra in digital circuit nor the nonlinear amplifying and filtering in analog circuit. Instead, it tightly brings together the algorithmatic essence of computing and the quantum-induced randomness through the powerful framework of stochastic-based computing transformation.

A Compact Adder and Reprogrammable Logic Gate Using Micro-Electromechanical Resonators With Partial Electrodes

Abstract: In this brief, the design principles and experimental demonstration of a compact full adder along with a reprogrammable 4-input logic gate are presented. The proposed solution for implementation of digital circuits is based on a clamped–clamped micro-beam resonator with multiple split electrodes, in which the logic inputs tune the resonance frequency of the beam. This technique enables re-programmability during operation, and reduces the complexity of the digital logic design significantly; as an example, for a 64-bit adder, only 128 micro-resonators are required, compared to more than 1500 transistors for standard complementary metal–oxide–semiconductor (CMOS) architectures. We also show that an optimized simulated micro-resonator-based full adder is 45 times smaller than a CMOS mirror adder in 65-nm technology. While the energy consumption of this early generation of micro-resonator logic gates is higher than the CMOS solutions, we show that by careful device optimization and shrinking of the dimensions, femtojoules energy consumption and MHz operation, required by Internet of Things applications, are attainable.

qGDR: A Via-Minimization-Oriented Routing Tool for Large-Scale Superconductive Single-Flux-Quantum Circuits

Abstract: Single-flux-quantum (SFQ) circuit technologies are promising digital circuit technologies with high-speed and extremely low-power characteristics. However, heavy wire routing tasks are finished either by considerable human effort or by commercial routing tools with few physical considerations for the SFQ circuits. In this paper, we present an integrated global and detailed router for the SFQ circuits, qGDR, which aims at reducing the impedance mismatch during signal transfer by minimizing the total number of used vias. The global router allocates routing resources while minimizing the via usage by a dynamic layer assignment algorithm. The detailed router follows the global routing results to complete the routing task by resorting to a maze routing algorithm. Following the MIT-LL SFQ5ee process technology, qGDR can use only two routing layers to route an 8-bit integer divider with more than 40 000 Josephson junctions in less than one hour.