Showing papers on "Electronic design automation published in 2009"

Analog Circuit Design in Nanoscale CMOS Technologies

Abstract: As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition Vsb > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as Vsb > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109 devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

Electronic Design Automation: Synthesis, Verification, and Test

Abstract: This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book. Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes Table of Contents Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:?Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

Fundamentals of algorithms

Abstract: Publisher Summary This chapter presents various fundamental algorithms to the electronic design automation (EDA) research and development—from the classic graphic theories, the practical heuristic approaches, and then to the theoretical mathematical programming techniques The chapter goes through the fundamentals of algorithms that are essential for the readers to appreciate the various EDA technologies Many of the EDA problems can be either represented in graph data structures or transformed into graph problems The most representative ones, in which the efficient algorithms have been well studied, are elaborated The readers should be able to use these graph algorithms in solving many of their research problems Heuristic algorithms that yield suboptimal, yet reasonably good results are usually adopted as practical approaches Several selected heuristic algorithms are also covered The mathematical programming algorithms, which provide the theoretical analysis for the problem optimality, are explored and the mathematical programming problems that are the most common in the EDA applications are focused on

Elastic Circuits

Abstract: Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. Elasticity can be implemented both synchronously and asynchronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques. Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.

HeMPS - a framework for NoC-based MPSoC generation

Abstract: Multi-Processor Systems-on-Chip (MPSoCs) are increasingly popular in embedded systems. Due to their complexity and huge design space to explore for such systems, CAD tools and frameworks to customize MPSoCs are mandatory. Some academic and industrial frameworks are available to support bus-based MPSoCs, but few works target NoCs as underlying communication architecture. A framework targeting MPSoC customization must provide abstract models to enable fast design space exploration, flexible application mapping strategies, all coupled to features to evaluate the performance of running applications. This paper proposes a framework to customize NoC-based MPSoCs with support to static and dynamic task mapping and C/SystemC simulation models for processors and memories. A simple, specifically designed microkernel executes in each processor, enabling multitasking at the processor level. Graphical tools enable debug and system verification, individualizing data for each task. Practical results highlight the benefit of using dynamic mapping strategies (total execution time reduction) and abstract models (total simulation time reduction without losing accuracy).

Closed-Loop Modeling in Future Automation System Engineering and Validation

Abstract: This paper presents a new framework for design and validation of industrial automation systems based on systematic application of formal methods. The engineering methodology proposed in this paper is based on the component design of automated manufacturing systems from intelligent mechatronic components. Foundations of such componentspsila information infrastructure are the new IEC 61499 architecture and the automation object concept. It is illustrated in this paper how these architectures, in conjunction with other advanced technologies, such as Unified Modeling Language, Simulink, and net condition/event systems, form a framework that enables pick-and-place design, simulation, formal verification, and deployment with the support of a suite of software tools. The key feature of the framework is the inherent support of formal validation techniques achieved on account of automated transformation among different system models. The paper appeals to developers of automation systems and automation software tools via showing the pathway to improve the system development practices by combining several design and validation methodologies and technologies.

Taming irregular EDA applications on GPUs

Abstract: Recently general purpose computing on graphic processing units (GPUs) is rising as an exciting new trend in high-performance computing. Thus it is appealing to study the potential of GPU for Electronic Design Automation (EDA) applications. However, EDA generally involves irregular data structures such as sparse matrix and graph operations, which pose significant challenges for efficient GPU implementations. In this paper, we propose high-performance GPU implementations for two important irregular EDA computing patterns, Sparse-Matrix Vector Product (SMVP) and graph traversal. On a wide range of EDA problem instances, our SMVP implementations outperform all published work and achieve a speedup of one order of magnitude over the CPU baseline. Upon such a basis, both timing analysis and linear system solution can be considerably accelerated. We also introduce a SMVP based formulation for Breadth-First Search and observe considerable speedup on GPU implementations. Our results suggest that the power of GPU computing can be successfully unleashed through designing GPU-friendly algorithms and/or re-organizing computing structures of current algorithms. Categories and Subject Descriptors J.6 [Computer-Aided Engineering]: Computer-Aided Design (CAD). D.1.3 [Concurrent Programming]: Parallel Programming. General Terms Algorithms, Design, Languages.

Model-Based Design for Embedded Systems

Abstract: The demands of increasingly complex embedded systems and associated performance computations have resulted in the development of heterogeneous computing architectures that often integrate several types of processors, analog and digital electronic components, and mechanical and optical componentsall on a single chip. As a result, now the most prominent challenge for the design automation community is to efficiently plan for such heterogeneity and to fully exploit its capabilities. A compilation of work from internationally renowned authors, Model-Based Design for Embedded Systems elaborates on related practices and addresses the main facets of heterogeneous Model-Based Design for embedded systems, including the current state of the art, important challenges, and the latest trends. Focusing on computational models as the core design artifact, this book presents the cutting-edge results that have helped establish Model-Based Design and continue to expand its parameters.The book is organized into three sections: Real-Time and Performance Analysis in Heterogeneous Embedded Systems, Design Tools and Methodology for Multiprocessor System-on-Chip, and Design Tools and Methodology for Multidomain Embedded Systems. The respective contributors share their considerable expertise on the automation of design refinement and how to relate properties throughout this refinement while enabling analytic and synthetic qualities. They focus on multi-core methodological issues, real-time analysis, and modeling and validation, taking into account how optical, electronic, and mechanical components often interface. Model-Based Design is emerging as a solution to bridge the gap between the availability of computational capabilities and our inability to make full use of them yet. This approach enables teams to start the design process using a high-level model that is gradually refined through abstraction levels to ultimately yield a prototype. When executed well, Model-Based Design encourages enhanced performance and quicker time to market for a product. Illustrating a broad and diverse spectrum of applications such as in the automotive aerospace, health care, consumer electronics, this volume provides designers with practical, readily adaptable modeling solutions for their own practice.

Embedded System Design: Modeling, Synthesis and Verification

Abstract: Embedded System Design: Modeling, Synthesis and Verification introduces a model-based approach to system level design. It presents modeling techniques for both computation and communication at different levels of abstraction, such as specification, transaction level and cycle-accurate level. It discusses synthesis methods for system level architectures, embedded software and hardware components. Using these methods, designers can develop applications with high level models, which are automatically translatable to low level implementations. This book, furthermore, describes simulation-based and formal verification methods that are essential for achieving design confidence. The book concludes with an overview of existing tools along with a design case study outlining the practice of embedded system design. Specifically, this book addresses the following topics in detail: . System modeling at different abstraction levels . Model-based system design . Hardware/Software codesign . Software and Hardware component synthesis . System verification This book is for groups within the embedded system community: students in courses on embedded systems, embedded application developers, system designers and managers, CAD tool developers, design automation, and system engineering.

Nonlinear Data Utilization: From Direct Data Lookup to Behavioral Modeling

Abstract: This paper presents a comprehensive study on the effective utilization of large-signal measurement data in the nonlinear computer-aided design (CAD) process. To achieve this goal two distinctive, yet mutually complementary, approaches have been integrated. Measured nonlinear data was, in the first instance, directly integrated into a nonlinear CAD simulator, and in the second instance, utilized for a direct extraction of behavioral model parameters. The formulation of the developed model is based on the polyharmonic distortion approach. The combination of both the direct utilization of nonlinear data and the subsequent model generation into an integrated nonlinear design procedure offers rapid, yet reliable, deployment of the CAD-based design environment for complex large-signal simulations.

Floating-Point FPGA: Architecture and Modeling

Abstract: This paper presents an architecture for a reconfigurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and bit-oriented operations, while parameterized and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating-point operations are used to implement datapaths. In order to facilitate comparison with existing FPGA devices, the virtual embedded block scheme is proposed to model embedded blocks using existing field-programmable gate array (FPGA) tools. This methodology involves adopting existing FPGA resources to model the size, position, and delay of the embedded elements. The standard design flow offered by FPGA and computer-aided design vendors is then applied and static timing analysis can be used to estimate the performance of the FPGA with the embedded blocks. On selected floating-point benchmark circuits, our results indicate that the proposed architecture can achieve four times improvement in speed and 25 times reduction in area compared with a traditional FPGA device.

Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs

Abstract: This paper presents a new approach to the design and analysis of NoC topologies which is based on the transaction-oriented communication methods of on-chip components. We propose two algorithms that attempt to meet the communication requirement of an on-chip application using a minimum number of network resources for the task, by generating application-specific topologies. In addition, to aid the design process of complex systems, the design method incorporates a form of predictive analysis which can estimate the degree of contention in a given system without performing detailed simulation. This predictive analysis method is used to determine the minimum frequency of operation for generated topologies, and is incorporated into the topology generation process. The proposed design method was tested using real-word applications, including an MPEG4 decoder and a multi-window display application. The generated topologies were found to offer similar or better performance when compared with regular topologies. However, the topologies generated by our method were more economical, using, on average, half the network resources of regular topologies.

Analog Layout Generator for CMOS Circuits

Abstract: In this paper, we present a new layout level automation tool for analog CMOS circuits, namely, analog layout generator (ALG). ALG is capable of generating individual or matched components as well as placement and routing. ALG takes performance considerations into account, optimizing the layout in each step. A distinguishing feature of the tool is primarily providing spectra of generation possibilities ranging from full custom to automatic generation. ALG is not only designed to work as a standalone tool but also implemented to be the final step of an analog automation flow. The flow supports circuit level specification in addition to layout level user specifications, so that it can be integrated into an analog automation system. Another feature of ALG is its interaction with a layout adviser tool, namely, YASA. YASA performs sensitivity simulations using a spicelike simulator providing sensitivities of performance parameters with respect to circuit parameters.

Synopsys' open educational design kit: Capabilities, deployment and future

Abstract: An open Educational Design Kit (EDK) which supports a 90nm design flow is described which includes all the necessary design rules, models, technology files, verification and extraction command decks, scripts, symbol libraries, and PCells. It also includes a Digital Standard Cell Library (DSCL) which supports all contemporary low power design techniques; an I/O Standard Cell Library (IOSCL); a set of memories (SOM) with different word and data depths; and a phase-locked loop (PLL). These components of the EDK augment any type of design for educational and research purposes. Though the EDK does not contain any foundry information, it allows real 90nm technology with high accuracy to be implemented in the designs.

DeltaSyn: an efficient logic difference optimizer for ECO synthesis

Abstract: During the IC design process, functional specifications are often modified late in the design cycle, after placement and routing are completed. However, designers are left either to manually process such modifications by hand or to restart the design process from scratch — a very costly option. In order to address this issue, we present DeltaSyn, a method for generating a highly optimized logic difference between a modified high-level specification and an implemented design. DeltaSyn has the ability to locate boundaries in implemented logic within which changes can be confined. Delta-Syn demarcates the boundary in two phases. The first phase employs fast functional and structural analysis techniques to identify equivalent signals forming the input-side boundary of the changes. The second phase locates the output-side boundary of the changes through a novel dynamic algorithm that detects matching logic downstream from the changes required by the ECO. Experiments on industrial designs show that together these techniques successfully implement ECOs while preserving an average of 97% of the existing logic. Unlike previous approaches, the use of bit-parallel logic simulation and fast SAT solvers enables high performance and scalability. DeltaSyn can process and verify a typical ECO for a design of around 10K gates in about 200 seconds or less.

Computer-aided design for microfluidic chips based on multilayer soft lithography

Abstract: Microfluidic chips are emerging as a powerful platform for automating biology experiments. As it becomes possible to integrate tens of thousands of components on a single chip, researchers will require design automation tools to push the scale and complexity of their designs to match the capabilities of the substrate. However, to date such tools have focused only on droplet-based devices, leaving out the popular class of chips that are based on multilayer soft lithography. In this paper, we develop design automation techniques for microfluidic chips based on multilayer soft lithography. We focus our attention on the control layer, which is driven by pressure actuators to invoke the desired flows on chip. We present a language in which designers can specify the Instruction Set Architecture (ISA) of a microfluidic device. Given an ISA, we automatically infer the locations of valves needed to implement the ISA. We also present novel algorithms for minimizing the number of control lines needed to drive the valves, as well as for routing valves to control ports while admitting sharing between the control lines. To the microfluidic community, we offer a free computer-aided design tool, Micado, which implements a subset of our algorithms as a practical plug-in to AutoCAD. Micado is being used successfully by microfluidic designers. We demonstrate its performance on three realistic chips.

Characterization of Asynchronous Templates for Integration into Clocked CAD Flows

Abstract: Asynchronous circuit design can result in substantial benefits ofreduced power, improved performance, and high modularity. However,asynchronous design styles are largely incompatible with clocked CAD,which has prevented wide-scale adoption. The key incompatibility istiming. Thus most commercial work relies on custom CAD or untimeddelay-insensitive design methodologies. This paper proposes a newmethodology, based on formal verification and relative timing, tocreate and prove correct necessary constraints to support asynchronousdesign with traditional clocked CAD. These constraints support timingdriving synthesis, place and route, and behavior and timing validationof fully asynchronous designs using traditional clocked CAD flows.This flow is demonstrated through a simple example pipeline in IBM's65nm process showing the ability to retarget the design for improvedpower and performance.

Software Methodologies for the Engineering of Service-Oriented Industrial Automation: The Continuum Project

Abstract: Service-orientation represents a new wave of features and solutions by bringing closer Information Technology to the industrial domain, particularly factory shop floors. The service-oriented automation software entities (designated here by bots) used in such approach requires a short set of methodologies and software targeting their specification for both computer systems and embedded automation devices. The present work explains the adopted methodologies and software developments for the engineering of service-based automation systems. The main contents focus on the specification of a framework for the development of bots and supporting engineering tools that are part of the Continuum project. The paper also does an overview over the engineering steps from the system design to the operation, and focuses the importance of the maintenance of automation bots. Such applications will contribute to decrease the development time and reduce the components' interdependency, offering enough flexibility for automatic reconfiguration of shop-floor layouts.

A Method and Software Tool for Automated Gearbox Synthesis

Abstract: In today’s economy, engineering companies strive to reduce product development time and costs. One approach to assisting this goal is to introduce computer-aided methods and tools earlier in the development process. This requires providing robust design automation methods and tools that can support design synthesis and the generation of alternative design configurations, in addition to automated geometric design. A new method for automated gearbox design, tailored for integration within an existing commercial gearbox analysis tool, is described in this paper. The method combines a rule-based generative approach, based on a previous parallel grammar approach for mechanical gear systems, with domain specific heuristics and stochastic search using simulated annealing. Given design specifications that include a bounding box, the number of required speeds and their target ratios, a range of valid gearbox configurations is generated from a minimal initial configuration. Initial test results show that this new method is able to generate a variety of designs which meet the design specifications. The paper concludes with a discussion of the method’s current limitations and a description of the work currently underway to improve and extend its capabilities.Copyright © 2009 by ASME

The road to 3D EDA tool readiness

Abstract: Today's SoCs/SIPs face numerous design challenges as increased integration of system components on a single die stretches the limits of technology and design capacity. 3D integration, where multiple dies are stacked and interconnected in the vertical dimension using through-silicon vias (TSVs), is probably the best hope for carrying ICs along (and even beyond) the path of Moore's law in the 21st century. However successful adoption of 3D ICs will require among other things modifications to EDA tools to enable 3D IC design. In this paper, we identify key stages in EDA that need modification to handle 3D ICs, highlight the challenges and review existing solutions, if they exist. Whenever appropriate, at a particular stage, we also provide preferred features of the solutions necessary to enable 3D IC design with the least amount of disruption.

ESL Models and their Application: Electronic System Level Design and Verification in Practice

Abstract: This book arises from experience the authors have gained from years of work as industry practitioners in the field of Electronic System Level design (ESL). At the heart of all things related to Electronic Design Automation (EDA), the core issue is one of models: what are the models used for, what should the models contain, and how should they be written and distributed. Issues such as interoperability and tool transportability become central factors that may decide which ones are successful and those that cannot get sufficient traction in the industry to survive. Through a set of real examples taken from recent industry experience, this book will distill the state of the art in terms of System-Level Design models and provide practical guidance to readers that can be put into use. This book is an invaluable tool that will aid readers in their own designs, reduce risk in development projects, expand the scope of design projects, and improve developmental processes and project planning.

Enabling concurrent clock and power gating in an industrial design flow

Abstract: Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way that the clock-gating information can be used to drive the control signal of the power-gating circuitry, thus providing additional leakage minimization conditions w.r.t. those manually inserted by the designer. This conceptual integration, however, poses several challenges when moved to industrial design flows. Although both clock and power-gating are supported by most commercial synthesis tools, their combined implementation requires some flexibility in the back-end tools that is not currently available. This paper presents a layout-oriented synthesis flow which integrates the two techniques and that relies on leading-edge, commercial EDA tools. Starting from a gated-clock netlist, we partition the circuit in a number of clusters that are implicitly determined by the groups of cells that are clock-gated by the same register. Using a row-based granularity, we achieve runtime leakage reduction by inserting dedicated sleep transistors for each cluster. The entire flow has been benchmarked on a industrial design mapped onto a commercial, 65nm CMOS technology library.

An Outlook on Design Technologies for Future Integrated Systems

Abstract: The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is paving the way to a new class of heterogeneous integrated systems, with increased performance and connectedness and providing us with gateways to the living world. This paper surveys design requirements and solutions for heterogeneous systems and addresses design technologies for realizing them.

SMT-based stimuli generation in the SystemC Verification library

Abstract: Modelling at the Electronic System Level (ESL) is the established approach of the major System-on-chip (SoC) companies. While in the past ESL design covered design methodologies only, today also verification and debugging is included. To improve the verification process, testbench automation has been introduced highlighted as constraint-based random simulation. In SystemC - the de facto standard modelling language for ESL - constraint-based random simulation is available through the SystemC Verification (SCV) library. However, the underlying constraint-solver is based on Binary Decision Diagrams (BDDs) and hence suffers from memory problems. In this paper, we propose the integration of new techniques for stimuli generation based on Satisfiability Modulo Theories (SMT). Since SMT solvers are designed to determine a single satisfying solution only, several strategies are proposed forcing the solver to generate more than one stimuli from different parts of the search space. Experiments demonstrate the advantage of the proposed approach and the developed strategies in comparison to the original BDD-based method.

Instrumenting AMS assertion verification on commercial platforms

Abstract: The industry trend appears to be moving towards designs that integrate large digital circuits with multiple analog/RF (radio frequency) interfaces. In the verification of these large integrated circuits, the number of nets that need to be monitored has been growing rapidly. Consequently, the mixed-signal design community has been feeling the need for AMS (Analog and Mixed Signal) assertions that can automatically monitor conformance with expected time-domain behavior and help in debugging deviations from the design intent. The main challenges in providing this support are (a) developing AMS assertion languages or AMS verification libraries, and (b) instrumenting existing commercial simulators to support assertion verification during simulation. In this article, we report two approaches: the first extends the Open Verification Library (OVL) to the AMS domain by integrating a new collection of AMS verification libraries; while the second extends SystemVerilog Assertions (SVA) by augmenting analog predicates into SVA. We demonstrate the use of AMS-OVL on the Cadence Virtuoso environment while emphasizing that our libraries can work in any environment that supports Verilog and Verilog-A. We also report the development of tool support for AMS-SVA using a combination of Cadence NCSIM and Synopsys VCS. We demonstrate the utility of both approaches on the verification of LP3918, an integrated power management unit (PMU) from National Semiconductors. We believe that in the absence of existing EDA (Electronic Design Automation) tools for AMS assertion verification, the proposed approaches of integrating our libraries and our tool sets with existing commercial simulators will be of considerable and immediate practical value.

Whole-chip ESD protection design verification by CAD

Abstract: CAD is essential to simulation, design and synthesis of on-chip ESD protection circuitry to ensure design prediction and verification at whole-chip level. This paper reviews a new function-based ESD CAD platform and design methodology, including arbitrary ESD protection device extraction algorithm, smart parametric ESD checking mechanism, smart ESD zapping simulation flow and new CAD tools enabling whole-chip ESD protection design verification. Practical design examples are presented.

A research roadmap for model-driven design of embedded systems for automation components

Abstract: The aim of this paper is to describe a research roadmap for a multi-domain model-driven embedded systems design approach and the corresponding meta-model which is applicable to the domain of complex Industrial Automation and Control Systems (IACS). The special requirements of the industrial automation sector are taken into account by this novel approach, utilizing existing model-driven techniques. This approach is currently being developed in the Framework Seven (FP7) Embedded Systems Design project MEDEIA funded by the European Commission.

Power estimation methodology for a high-level synthesis framework

Abstract: As adoption of system-level hardware design is increasing in industry and academia, accurate power estimation at this level is becoming important. In this paper, we present a system-level power estimation methodology, which is based on a high-level synthesis framework and supports sufficiently accurate power estimation of hardware designs at the systemlevel. For early and accurate power estimation, the proposed methodology utilizes register transfer level (RTL) probabilistic power estimation technique controlled by the system-level simulation. Furthermore, our methodology does not require a designer to move to the traditional RTL power estimation methodology, thus facilitating easy and early power analysis and aiding the cause of adoption of system-level design practices in ASIC design flow. This paper provides detailed description of our methodology including tools used, algorithm for extracting activity from system-level value change dump and finally mapping this information for RTL power estimation. We show the usefulness of our approach by performing power estimation on synthesizable cycle-accurate transaction-level (CATL) design models of reasonable complexity such as prototype processor model (VeSPA processor), universal asynchronous receiver and transmitter (UART), FFT filter, etc. We demonstrate our methodology through industry standard EDA tools used in the ASIC design flow and show that the loss in accuracy for the proposed approach with respect to the state-of-the-art RTL power estimation techniques ranges from 3?9%. The speed up gained using our approach is upto 12 times more than RTL simulation based power estimation approach.

Towards Model-Based Integration of Tools and Techniques for Embedded Control System Design, Verification, and Implementation

Abstract: While design automation for hardware systems is quite advanced, this is not the case for practical embedded systems. The current state-of-the-art is to use a software modeling environment and integrated development environment for code development and debugging, but these rarely include the sort of automatic synthesis and verification capabilities available in the VLSI domain. We present a model-based integration environment which uses a graphical architecture description language (EsMoL) to pull together control design, code and configuration generation, platform-specific simulation, and a number of other features useful for taming the heterogeneity inherent in safety-critical embedded control system designs. We describe concepts, elements, and development status for this suite of tools.