Showing papers on "Field-effect transistor published in 1982"

MOS /metal oxide semiconductor/ physics and technology

Abstract: Introduction. Field Effect. Metal Oxide Silicon Capacitor at Low Frequencies. Metal Oxide Silicon Capacitor at Intermediate and High Frequencies. Extraction of Interface Trap Properties from the Conductance. Interfacial Nonuniformities. Experimental Evidence for Interface Trap Properties. Extraction of Interface Trap Properties from the Capacitance. Measurement of Silicon Properties. Charges, Barrier Heights, and Flatband Voltage. Charge Trapping in the Oxide. Instrumentation for Measuring Capacitor Characteristics. Oxidation of Silicon--Oxidation Kinetics. Oxidation of Silicon--Technology. Control of Oxide Charges. Models of the Interface. Appendices. Subject Index. Symbol Index.

Heterostructure bipolar transistors and integrated circuits

Abstract: Two new epitaxial technologies have emerged in recent years (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)), which offer the promise of making highly advanced heterostructures routinely available. While many kinds of devices will benefit, the principal and first beneficiary will be bipolar transistors. The underlying central principle is the use of energy gap variations beside electric fields to control the forces acting on electrons and holes, separately and independently of each other. The resulting greater design freedom permits a re-optimization of doping levels and geometries, leading to higher speed devices. Microwave transistors with maximum oscillation frequencies above 100 GHz and digital switching transistors with switching times below 10 ps should become available. An inverted transistor strucure with a smaller collectors on top and a larger emitter on the bottom becomes possible, with speed advantages over the common "emitter-up" design. Double-heterostructure (DH) transistors with both wide-gap emitters and collectors offer additional advantages. They exhibit better performance under saturated operation. Their emitters and collectors may be interchanged by simply changing biasing conditions, greatly simplifying the architecture of bipolar IC's. Examples of heterostructure implementations of I2L and ECL are discussed. The present overwhelming dominance of the compound semiconductor device field by FET's is likely to come to an end, with bipolar devices assuming an at least equal role, and very likely a leading one.

Semiconductors for high‐voltage, vertical channel field‐effect transistors

Abstract: The influence of material parameters upon the characteristics of vertical channel power field effect transistors is examined. It is demonstrated that for devices with the same breakdown voltage and device structure, the on‐resistance is inversely proportional to the third power of the energyband gap and inversely proportional to the mobility. In addition the frequency response of these devices increases in proportion to the mobility and the energyband gap. Calculated device parameters for III–V semiconductor compounds, as well as their alloys, have been compared to those of a silicondevice with the same breakdown voltage. It is found that devicesfabricated from GaAs,InP, and GaP are expected to have a current handling capability which is a factor of 12.7, 5, and 1.85 better than that of the silicondevice with the same breakdown voltage. In addition, the current handling capability of devicesfabricated from the alloy semiconductors GaAlAs, GaAsP, and InGaP are even superior to those of a GaAsdevice with the same breakdown voltage.

Model for modulation doped field effect transistor

Abstract: A model describing C-V and I-V characteristics of modulation doped FET's is proposed. The model takes into account the change in the Fermi energy with the gate voltage. At high two dimensional electron concentrations, the equations of the model for the charge control by the gate voltage become similar to the equations of the charge control model where the thickness d of AlGaAs layer should be substituted by d + Δ d and Δ d is the effective width of the potential well (≃ 80 A). Another important prediction of the model is the existence of the "subthreshold" current. A very good quantitative agreement is obtained with our experimental I-V curves using the measured values of the low field mobility and the source resistance.

Fabrication of high-performance LDDFET's with Oxide sidewall-spacer technology

Abstract: A fabrication process for the Lightly Doped Drain/Source Field-Effect Transistor, LDDFET, that utilizes RIE produced SiO 2 sidewall spacers is described. The process is compatible with most conventional polysilicon-gated FET processes and needs no additional photomasking steps. Excellent control and reproducibility of the n-region of the LDD device are obtained. Measurements from dynamic clock generators have shown that LDDFET's have as much as 1.9X performance advantage over conventional devices.

An analytical breakdown model for short-channel MOSFET's

Abstract: Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.

Submicrometer MOSFET structure for minimizing hot-carrier generation

Abstract: This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO 2 energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.

Velocity-Modulation Transistor (VMT) : A New Field-Effect Transistor Concept

Abstract: Field-effect transistors of a completely new category are proposed and analysed, in which the conductivity modulation ΔG by the gate voltage Vg is brought forth mainly through the Vg-dependence of electron mobility. Since the sheet concentration of electrons in such FETs need not be modulated, the switching speed of the device is expected to be free from the transit time limitation, reaching the range of subpicosecond. As a specific example, an FET with a dual-channel configuration is discussed.

A transmission line model for silicided diffusions: Impact on the performance of VLSI circuits

Abstract: In scaled technologies, performance improvements become increasingly limited by interconnect parasitics. The increased emphasis in the literature on low-resistance replacements for, or supplements to, polysilicon-gate technologies verifies the importance of parasitic limitations. Further, the role of the series source and drain resistance as well as contact resistance in limiting device performance has also been addressed by several authors. This role is further enhanced by the actual much more rapid increase in sheet resistivity with decreasing junction depth than previously assumed by other workers. In fact, it can be anticipated that metallurgical advances, such as silicides, will be required to compensate for the increased sheet resistance of source and drain diffusions. In the present work, a theoretical development of a transmission line model for a totally silicided diffusion is presented. Both the silicide and the diffusion sheet resistivities ρ S and ρ D , and the specific contact resistivity ρ c , are incorporated, unlike earlier models for contact holes only in which ρ S = 0. This model is applied to specific typical MOS structures, including single-section and three-section structures, to calculate the contact resistance contribution to total resistance. These results are used in conjunction with device equations addressing the device and circuit performance of small-geometry MOSFET's. Both n- and p-channel devices are considered as well as various scaling scenarios (constant field, constant voltage, etc.). These results show that for n-channel devices with a gate length of 1 µm, a-factor-of-two increase in circuit performance can be expected when using silicides. However, for p-channel devices, the expected performance gain as a result of using silicides is a factor of ten.

Junction field-effect transistor controlled by merged depletion regions

Abstract: A new method of semiconductor operation has been conceived, developed and applied to produce a revolutionary new semiconductor design. The method is that of merging depletion regions for purposes of operation, isolation and control of channel current in a junction field-effect transistor. Using this method depletion regions are made to merge with suitable biasing in an intervening layer interposed between the gate and channel of a junction field-effect device and the interaction of the depletion regions is used for isolation and coupling to alter the associated depletion region in the channel of the junction field-effect device. A number of embodiments are disclosed of the new junction field-effect transistor controlled by merged depletion regions. In each embodiment a channel of one conductivity type material is formed in a semiconductor body of opposite type material. A gate region of the same conductivity type material as the channel is placed near enough to the channel so that when the gate junction is reversed bias, the gate depletion region merges with the channel junction depletion region in the intervening layer. When the two depletion regions have merged, the gate controls the channel current in a manner similar to conventional devices. Because the output and input and control connections are of the same conductivity type material, no metal contacts or interconnections are required. The lack of need for metal interconnects makes the device better suited to integrated circuits than any other device. In addition, the depletion regions surrounding the gate and channel isolate the gate and channel from other semiconductor regions of the same conductivity type and thus isolation regions are not required for the junction field-effect transistor controlled by mergers depletion regions. Consequently, use of the invention can result in the densest form of logic available today. Such devices hold the promise of improved performance in almost every semiconductor device application and can be used in almost every application where MOS and junction field-effect devices are now used.

Proton isolation for GaAs integrated circuits

Abstract: Significant improvement in the electrical isolation of closely spaced GaAs integrated circuit (IC) devices has been achieved with proton implantation. Isolation voltages have been increased by a factor of four in comparison to a selective implant process. In addition, the tendency of negatively biased ohmic contacts to reduce the current flow in neighboring MESFET's (backgating) has been reduced by at least a factor of three. The GaAs IC compatible process includes implantation of protons through the SiO 2 field oxide and a three-layered dielectric-Au mask which is definable to 3-µm linewidths and is easily removed. High temperature storage tests have demonstrated that proton isolation, with lifetimes on the order of 106h at 290°C, is not a lifetime limiting component in a GaAs IC process.

Offset-gate chemical-sensitive field-effect transistors (OG-CHEMFETS) with electrolytically-programmable selectivity

Abstract: A selective chemosensitive microelectronic transducer is provided for the detection and measurement of chemical properties, by engineering a field-effect transistor such that source 6 and drain 7 regions are connected to bonding pads 2 and 4, and the semiconductor bulk connected to pad 1. The metal gate 8 is extended laterally to a remote area 9, and also to bonding pad 3 via a narrow metallization track 5 designed to support only a limited, predetermined electrical current in the manner of a fusible link. External electrical access to the device is achieved with wirebonding 14, and the device is selectively sealed with an inert, impervious encapsulation material 10 such that only gate area 9 remains exposed. Electroactive materials are deposited over the offset-gate area 9, or electrodeposited using connection through 8, 5 and 3. Subsequently, link 5 is open-circuited by pulsed electrical overload, creating a floating chemosensitive gate.

Channel-collector transistors

Abstract: By merging the channel regions of two-junction field-effect transistors with the collector region of a bipolar junction transistor (BJT), one achieves a quasi-cascode configuration called a Channel-Collector Transistor (CCT). Its terminal properties are those of a modified, improved bipolar transistor. Prototype devices have been fabricated with common-emitter current gain (β F ) in excess of 1200 while still maintaining the common-emitter, open-base breakdown voltage (BV CE0 ) greater than 140 V and the output resistance r 0 typically greater than 200 kΩ. The present brief describes an efficient, qualitative equivalent circuit for the structure and also presents an experimental device graphically illustrating the CCT's advantages and disadvantages when compared to a conventional BJT.

Self-align implantation for n+-layer technology (SAINT) for high-speed GaAs ICs

Abstract: A new GaAs MESFET structure with n+-implanted layers and a self-aligned gate has been developed by dielectric lift-off technology with trilevel resist. The electrical characteristics are improved greatly by resistance reduction outside the channel under the gate. 280 mS/mm transconductance and 39.5 ps/gate propagation delay have been obtained.

Common memory gate non-volatile transistor memory

Abstract: A non-volatile semiconductor memory is described incorporating a fixed threshold transistor and a variable threshold transistor in each memory cell. The fixed threshold transistor is used for row selection while the variable threshold transistor stores the data. A common memory gate line throughout the memory permits block erase to one logic state with opposite data being written in on a row-by-row basis. Information is read out from a selected row by a ramp voltage on the memory gate line which is capacitively coupled through variable threshold transistors having a channel in the body below the gate region.

Fast Timing Methods for Semiconductor Detectors

Abstract: This tutorial paper discusses the basic parameters which determine the accuracy of timing measurements and their effect in a practical application, specifically timing with thin-surface barrier detectors. The discussion focusses on properties of the detector, low-noise amplifiers, trigger circuits and time converters. New material presented in this paper includes bipolar transistor input stages with noise performance superior to currently available FETs, "noiseless" input terminations in sub-nanosecond preamplifiers and methods using transmission lines to couple the detector to remotely mounted preamplifiers. Trigger circuits are characterized in terms of effective rise time, equivalent input noise and residual jitter.

CCD Demodulator circuit

Abstract: A semiconductor integrated circuit using charged coupled device (CCD) technology for performing demodulation of time-varying signals which have been phase or amplitude modulated. The CCD circuit performs a sampling of the time-varying signal at a suitable sampling frequency depending upon the frequency of the phase or amplitude modulation of the carrier. The CCD device converts the sample into an equivalent charge packet which is used to control the control electrode of a field effect transistor in an amplifier circuit. The magnitude of the sample is representative of the amplitude of the carrier so that the output of the field effect transistor represents a demodulated signal. The circuit is a broad spectrum device, operable with a signal frequency from the audio into the gigaHertz (GHz) frequency range.

GaAs LSI-directed MESFET's with self-aligned implantation for n + -layer technology (SAINT)

Abstract: Self-aligned implantation for n+-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n+-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-law I - V fitting has been improved by a factor of 3.4, compared to conventional FET's without the n+-layer. Thermal emission for carriers from the source n+-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.

Correlation between substrate and gate currents in MOSFET's

Abstract: A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.

Microwave Wide-Band Model of GaAs Dual Gate MESFET's

Abstract: A multioctave model of GaAs dual gate MESFET's is presented. It consists of 28 frequency independent elements and is valid between 2 and 11 GHz. Dual gate FET's with and without intergate ohmic contact have been considered. The modeling method utilized consists in separate dc and HF characterization and equivalent circuit determination of the active device parts in their actual bias conditions. Thereby, two goals are obtained : a) The topology of the overall model can be derived from well-known simpler, partial ones; and b) the starting values of optimization are precise enough to allow reliable physical solutions.

Impact ionization at very low voltages in silicon

Abstract: Impact ionization in germanium and silicon has been the subject of extensive theoretical and experimental work. The general agreement in the literature for the value of the threshold energy for impact ionization is 1.5 times the energy gap (EG) at room temperature which corresponds to 1.65 eV in the case of silicon. In this work, using a metal semiconductor field effect transistor (MOS device), as a sensitive tool for detecting small multiplication currents, impact ionization is investigated in a region where the total potential drop over which carriers are accelerated is less than the threshold energy for impact ionization. Impact ionization currents are detected for potential drop as low as 1.1 V. The positive temperature coefficient in this region suggests that the initial thermal distribution of the electrons dominates impact ionization for very low accelerating voltages.

Field effect transistor with high cut-off frequency and process for forming same

Abstract: There is disclosed a heterojunction field effect transistor with an accumulation of majority carriers functioning as a high cut-off frequency device in which the transistor uses the properties of the same type GaAs/Al x Ga 1-x As N-doped junctions with the GaAs being weakly doped. This is used to produce a high mobility of charges in the accumulation layer and is effected by a structure in which the source and drain regions are partially covered by the gate region which is in turn covered by an insulation layer and thereby reduces the access resistances and increases the transition frequencies.

Insulated gate field effect transistor

Abstract: Insulated gate field effect transistor having a surface zone (6) ("extended drain') adjoining the drain zone, said surface zone being of the same conductivity type as the drain zone but with lower doping. According to the invention the field effect transistor is provided in an epitaxial layer (3) which is present on a substrate (11) of the opposite conductivity type. Below the channel region (7) and the surface zone (6) a buried layer (12) of the same conductivity type as the epitaxial layer is present. Above the surface zone (6) a field plate (10) is provided, which field plate is preferably connected to the source electrode (4) or to the gate electrode (8) and is separated from the semiconductor surface by an insulating layer (13) having a thickness increasing in the direction of the drain zone. As a result of this the surface zone (6) is pinched off progressively and higher drain voltages are possible. The epitaxial layer (3) is preferably depleted by the RESURF principle.

Insulated-gate field-effect transistors

Abstract: An insulated-gate field-effect transistor which may be of a vertical power D-MOS type comprises surface-adjacent source and emitter regions (10 and 15) surrounded in a semiconductor body (1) by a surface-adjacent second region (20) of opposite conductivity type. A third region (30) adjoins the second region and has a lower conductivity-type determining doping concentration. At least a part of these second and third regions is located in a main current path from the source region (10) to a drain (31) of the transistor, and an insulated gate (4) which may be of metal-silicide capacitively controls a conductive channel at least in this part (21) of the second region (20). The emitter region (15) is located at a side of the source region (10) remote from the channel part (21) and is separated therefrom by an intermediate part (22) of the second region (20). The source region is electrically connected to this intermediate part (22), for example by a short-circuiting metal-silicide layer (8). A resistive current path (25) in the second region (20) is present below the emitter region (10) and extends from this intermediate part (22) to a further part (23) of the second region (20) which is electrically connected to the emitter region (15), for example by a short-circuiting metal-silicide layer (9). A source electrode (2) is electrically connected to this further part (23) so as to be electrically connected via the resistive current path (25) to the source region (10). The emitter region (15) serves to modulate the conductivity of the third region (30) and so reduce the drain series resistance of the transistor, by charge-carrier injection from the intermediate part (22) when the source-drain current along the resistive current path (25) is sufficient to forward-bias the intermediate part (22) with respect to the third region (30).

Insulated gate field effect transistor

Abstract: An insulated gate field effect transistor formed in one surface of a semiconductor substrate (1) has a channel, the surface portion of which has an impurity (9) with a conductivity type opposite to that of the substrate (1), and the deeper portion of which has an impurity (8) of the same conductivity type to the substrate. Moreover, the source and/or the drain (6, 7) of the transistor has an impurity layer of a conductivity type opposite to that of the substrate, with an impurity distribution (13, 14) gently sloped. The use of such impurity distributions overcomes the problems of the short-channel effect and reduction of the source-drain breakdown voltage which are present in standard devices. This enables a shorter channel to be used for a given source-drain breakdown voltage which is of advantage in a LSI having a high density of integration.

Power MOSFET temperature measurements

Abstract: Three temperature-sensitive electrical parameters are compared as thermometers for power MOSFET devices. The parameters are the forward drain-body diode voltage, the source-gate voltage, and the on-resistance. The results are also compared with temperatures measured with an infrared microradiometer. The procedure, apparatus, and circuits required to use each of the parameters as a thermometer are described. Some general considerations for measuring the temperature of power semiconductor devices are also discussed. Each parameter is found to be satisfactory for measuring the temperature of power MOSFETs. The sourcegate voltage measures a temperature nearest to the peak device temperature, and the drain-body diode voltage shows the least variation in calbiration from device to device.

Overcurrent limiter circuit for switching regulator power supplies

Abstract: A circuit is disclosed which provides overcurrent protection for switching regulator power supplies with soft start and soft turn OFF features. The invention includes first means for sensing the current through the switching transistor of the regulator and second means for providing a voltage signal to the switching transistor deactivation circuitry whenever the current through the switching transistor exceeds a predetermined threshold. In a specific embodiment, the current generator is provided by a transistor biased for nominal operation in its active mode. The means for sensing the current through the switching transistor is provided by a resistor the voltage drop across which provides the input voltage threshold to the bipolar transistor current generator. The current generated by the transistor causes a voltage to quickly develop across an RC network referenced to ground potential. This voltage is then compared to a reference potential by a comparator circuit which provides an electrical signal as an input to the base drive circuit for the switching regulator switching transistor.