Showing papers on "MOSFET published in 1985"
TL;DR: In this article, it was shown that MOSFET degradation is due to interface states generation by electrons having 3.7 eV and higher energies, and this critical energy and the observed time dependence was explained with a physical model involving the breaking of the = Si/sub s/H bonds.
Abstract: Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with a physical model involving the breaking of the = Si/sub s/H bonds. The device lifetime /spl tau/ is proportional to...
643 citations
TL;DR: In this paper, the authors demonstrate that deviations from 1/f noise behavior found in submicron silicon metaloxide-semiconductor field effect transistors operating at room temperature are the direct result of the decomposition of the 1/F spectrum into its constituent Lorentzian components.
Abstract: We demonstrate that deviations from 1/ f noise behavior found in submicron silicon metal‐oxide‐semiconductor field‐effect transistors operating at room temperature are the direct result of the decomposition of the 1/ f spectrum into its constituent Lorentzian components. In the time domain, these devices produce random telegraph signals due to localized and discrete modulations of the channel resistance caused by individual carrier trapping events.
283 citations
TL;DR: The anomalous leakage current I L in LPCVD polysilicon MOSFETs is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed.
Abstract: The anomalous leakage current I L in LPCVD polysilicon MOSFET's is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce I L , and indicates when the back-surface leakage component is significant.
275 citations
TL;DR: In this paper, a design methodology was developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools.
Abstract: Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.
231 citations
TL;DR: In this paper, an exact SOI device simulator applicable to prediction of the transistor characteristics in high-current region is developed, where the basic Poisson's and current continuity equations are numerically solved under steady-state condition.
Abstract: An exact SOI device simulator applicable to prediction of the transistor characteristics in high-current region is developed. In the simulator, the basic two-dimensional Poisson's and current continuity equations are numerically solved under steady-state condition. To obtain a stable and rapid convergence in the numerical scheme, a newly developed alternative step solving method is implemented. Using this simulator, the drain current kink effect, a typical phenomenon for substrate-floating devices, is exactly simulated for the first time. The physical mechanism of this phenomenon is also clarified. The simulated results indicate that kink effects are suppressed by using low-lifetime SOI substrates.
92 citations
TL;DR: In this article, a modified McWhorter model has been developed to explain the mechanisms involved in the 1/f noise in n-channel metal-oxide, semiconductor field effect transistors (MOSFETs).
Abstract: A modified McWhorter model has been developed to explain the mechanisms involved in the 1/f noise in n-channel metal-oxide, semiconductor field-effect transistors (MOSFET's). Under the assumption of an energy distribution of traps in the bandgap, an expression for the power spectral density of 1/f noise was derived for MOSFET's operating in the linear region. Experimentally, noise measurements were performed on short-channel enhancement-mode MOSFET's with gate widths of 100 µm, and varying gate lengths of 2 to 10 µm. It was found that noise power increased with increasing drain voltage or decreasing gate bias. Quantitative analyses have been done to compare the experimental results with the model calculations.
90 citations
TL;DR: In this paper, a systematic method is given for generating negative-resistance circuits made of 2 transistors and linear positive resistors only, which can be integrated as a two-terminal device in monolithic form.
Abstract: A systematic method is given for generating negative-resistance circuits made of 2 transistors and linear positive resistors only. The 2 transistors may be bioolar ( n-p-n or p-n-p ), JFET ( n -channel or p-channel), MOSFET ( n -channel or p -channel), or their combinations. Since the circuits do not require an internal power supply, they are passive and can be integrated as a two-terminal device in monolithic form. Two algorithms are given for generating a negative-resistance device which exhibits either a type- N \upsilon - i characteristic similar to that of a tunnel diode, or a type- S \upsilon -i characteristic similar to that of a four-layered p-n-p-n diode. Hundreds of new and potentially useful negative resistance devices have been discovered. A selected catalog of many such prototype negative-resistance devices is included for future applications.
89 citations
Patent•
11 Oct 1985
TL;DR: In this article, a high voltage generator is used for writing or erasing a memory cell while maintaining fixedly a substrate potential constant by forming capacities connected alternately with the gates of MNOS elements and high voltage generators by a pair of MOSFETs.
Abstract: PURPOSE:To enable to apply a high voltage for writing or erasing a memory cell while maintaining fixedly a substrate potential constant by forming capacities connected alternately with the gates of MNOS elements and high voltage generators by a pair of MOSFET CONSTITUTION:A peripheral circuit is formed of C-MOS logic circuits, a high voltage generator 26 for applying a voltage for writing or erasing to a MNOS element Qm of memory cell, a pair of MOSFETQ1, Q2 complementarily driven to be conducted at writing or erasing time, and a capacity C connected alternately with the gate G of the element Qm and the generator 27 by the MOSFETs Q1, Q2 are provided Further, the output voltage -Vpp from the generator 26 is applied to between the well 12 and the gate G, and the one is connected with the ground potential or the power source potential -Vpp
71 citations
TL;DR: It was observed that the feedthrough voltage decreases linearly with the input voltage, a significance of this observation when considering harmonic distortion in sample-and-hold circuits is discussed.
Abstract: Charge feedthrough in analog MOS switches has been measured. The dependence of the feedthrough voltage on the input and tub voltages, device dimensions, and load capacitances was characterized. Most importantly, it was observed that the feedthrough voltage decreases linearly with the input voltage. The significance of this observation when considering harmonic distortion in sample-and-hold circuits is discussed. A first-order computer simulation based on the quasi-static small-signal MOSFET capacitances shows good agreement with experimental results.
67 citations
Patent•
11 Mar 1985TL;DR: In this article, a self-oscillating power converter utilizes a MOSFET power transistor switch with its output electrode coupled to a tuned network that operatively limits the voltage waveform across the power switch to periodic unipolar pulses.
Abstract: A self-oscillating power converter utilizes a MOSFET power transistor switch with its output electrode coupled to a tuned network that operatively limits the voltage waveform across the power switch to periodic unipolar pulses. The transistor switch may be operated at a high radio frequency so that its drain to gate interelectrode capacitance is sufficient to comprise the sole oscillatory sustaining feedback path of the converter. A reactive network which is inductive at the operating frequency couples the gate to source electrodes of the transistor switch and includes a variable capacitance as a means of adjusting the overall reactance, and hence the converter's switching frequency in order to provide voltage regulation. A resonant rectifier includes a tuned circuit to shape the voltage waveform across the rectifying diodes as a time inverse of the power switch waveform.
61 citations
TL;DR: In this article, the principal parameters for short-channel MOSFETs were derived from the experimental curves ID(VG) and ID(VD) curves. But the main assumption is that the devices fabricated on the same silicon chip have the same technological reduction of transistor channel length and the same series resistance of source and drain.
Abstract: In this paper we present a new method of determining the principal parameters for short-channel MOSFET modelling: VT, μ0, θ, ΔL and RSD. They are deduced from the experimental curves ID(VG) (for small drain voltages) and ID(VD) (for relatively large gate voltages) curves. The main assumption is that the devices fabricated on the same silicon chip have the same technological reduction of transistor channel length and the same series resistance of source and drain. Our method takes advantageously into account (a) a new accurate determination of the threshold voltage and (b) the variation of the low-field mobility with channel length. Results obtained by applying this method to short-channel devices are given and discussed.
TL;DR: In this article, a model based upon a MOSFET driving a wide-base p-np transistor is presented for analysis of the turnoff behavior of n-channel insulated gate transistors.
Abstract: A model based upon a MOSFET driving a wide-base p-n-p transistor is presented for analysis of the turn-off behavior of n-channel insulated gate transistors. This model is found to provide a very good quantitative explanation of the shape of the collector current waveform during turn-off. Verification was accomplished using insulated gate transistors (IGT's) fabricated with two voltage ratings and a variety of radiation doses. This analysis allows the separation of the channel (electron) and minority carrier (hole) current flow in the IGT for the first time.
TL;DR: In this article, the authors present electrical measurements of threshold voltage on matched transistor pairs which show a channel shortening effect due to the presence of dislocations or metallic precipitates in the device.
Abstract: In this letter we present electrical measurements of threshold voltage on matched transistor pairs which show a channel shortening effect due to the presence of dislocations or metallic precipitates in the device. Such effects could present a limitation on the yield and performance of MOS integrated circuits employing short-channel devices.
TL;DR: In this paper, the compatibility of GaAs with Si N-channel metaloxide-semiconductor (NMOS) transistors was demonstrated by successfully fabricating GaAs/AlGaAs modulation-doped field effect transistors (MODFETs) on a Si wafer containing NMOS devices.
Abstract: We have demonstrated for the first time the compatibility of GaAs with Si N‐channel metal‐oxide‐semiconductor (NMOS) transistors by successfully fabricating GaAs/AlGaAs modulation‐doped field‐effect transistors (MODFET’s) on a Si wafer containing NMOS devices. The MODFET’s with 2 μ gate length on 6 μ channels exhibited transconductances of 120 and 180 mS/mm at 300 and 77 K, respectively. The NMOS devices exhibited little if any performance degradation in going through the GaAs growth and fabrication process. These results show that the monolithic integration of GaAs devices with Si devices is possible, which may add a new dimension to the already exploding world of electronics.
Patent•
22 Feb 1985TL;DR: In this paper, a tri-state circuit consisting of a pre-stage circuit coupled to receive an input signal and an output stage, where an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage.
Abstract: A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN. Under this condition, the output terminal OUT is in a floating state. Thus, the switching circuit is a tri-state circuit.
TL;DR: In this paper, high-resolution ac measurements of drain conductance at low temperatures have been made on silicon MOSFET's with channels as narrow as 1 µm, showing discrete switching events in the channel resistance associated with individual electrons being captured and emitted from single interface traps.
Abstract: High-resolution ac measurements of drain conductance at low temperatures have been made on silicon MOSFET's with channels as narrow as 01 µm These devices show discrete switching events in the channel resistance associated with individual electrons being captured and emitted from single interface traps The voltage and temperature dependence of this switching gives detailed information on the characteristics of the trap and its distance from the interface This switching is a component of low-frequency noise in MOSFET's and may be an important limit to the performance of small transistors
Patent•
08 Aug 1985TL;DR: In this article, a MOS-type field effect transistor with a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is presented.
Abstract: Disclosed herein is a MOS-type field-effect transistor in which a semiconductor region having the same type of conductivity as the substrate and an impurity concentration higher than that of the substrate is formed under the channel so as to come at both ends thereof into contact with the source and drain regions. The semiconductor region restricts the extension of depletion layer from the source and drain regions, and restricts the short-channel effect. The junction capacity is small between the semiconductor region and the source and drain regions.
TL;DR: In this article, a charge-based large-signal model for thin-film SOI MOSFETs is proposed for computer simulation of transient characteristics of SOI and 3D circuits emphasizing the structural uniqueness of the devices.
Abstract: A charge-based large-signal model for thin-film SOI (Si-on-SiO 2 ) MOSFET's, intended for computer simulation of transient characteristics of SOI and 3-D circuits, is developed emphasizing the structural uniqueness of the devices. Closed-form expressions for the quasi-static terminal charges, simpler than those for the bulk MOSFET because of the thin-film structure, are derived in terms of terminal voltages and device parameters, and are used to define the terminal currents. Equivalent circuits, developed from the charge-based model, show that the device can be accurately represented using only real reciprocal capacitances by explicitly accounting for the transient channel transport current I TT . The analytic expression for I TT , obtainable for the thin-film structure, enables the evaluation of the finite-carrier transit delay in the channel and of the corresponding charge nonconservation in the conventional reciprocal-capacitance MOSFET model that does not account for the delay.
TL;DR: In this paper, an n+n-double-diffused drain MOS transistor was used to suppress hot-carrier emission. But the results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region.
Abstract: Channel electric field reduction using an n+-n-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.
Patent•
15 Oct 1985
TL;DR: In this paper, a temperature compensated complementary metal-insulator-semiconductor oscillator receives a temperature independent reference voltage from an external source, attenuated and summed with a threshold voltage in order to bias a gate electrode of MOSFET.
Abstract: A temperature compensated complementary metal-insulator-semiconductor oscillator receives a temperature independent reference voltage from an external source. The temperature independent reference voltage is attenuated and summed with a threshold voltage in order to bias a gate electrode of MOSFET. A bipolar p-n junction diode is connected to the MOSFET at a source electrode in order to bias the MOSFET with a temperature dependent forward voltage drop to compensate for temperature variations therein. The MOSFET controls a temperature independent current. A current mirror assembly receives the current and controls a Schmitt trigger oscillator. The Schmitt trigger oscillator generates a signal having a temperature independent constant period.
TL;DR: In this article, a design methodology was developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools.
Abstract: Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.
TL;DR: In this paper, the effect of interface parameters on the back and front threshold voltages is analyzed in case of a strong coupling between front and back interface (lightly doped epi layer).
Abstract: We consider SOI MOSFET structures ( N and P type) for which a control of the back potential of the epi layer is obtained by using a back gate. The effect of interface parameters on the back and front threshold voltages is analysed in case of a strong coupling between front and back interface (lightly doped epi layer). This analysis is carried out by a numerical integration of Poisson's equation throughout the structure. We thus obtain the potential profile, and the electron and hole densities, as a function of the applied front ( V g1 and back ( V g2 ) gate voltages. We also derive the I d ( V g1 , V g2 ) characteristics in the case of l drain voltage. This program allows us to examine the dependence of both front and back threshold voltages on the interfacial parameters. It is also used to examine the validity of the existing analytical models and to interpret experimental results obtained on MOS/SOS transistors.
TL;DR: In this paper, the backside gate bias was used as a parameter to measure the transconductance of n-channel SOI MOSFETs and the authors used the numerical solution of Poisson's equation to model the performance of SOI transistors.
Abstract: Transconductance of n-channel Silicon-on-Insulator (SOI) MOSFET's has been measured with backside gate (substrate) bias as a parameter For negative values of the backside gate bias, transconductance of SOI transistors is similar to that of bulk devices On the other hand, transconductance exhibits an unusual behavior when backside gate is positively biased This is caused by mutual influence between the front-and the backside gate-related depletion zones Modeling of transconductance using numerical solution of Poisson's equation show good agreement with experimental results
Patent•
19 Apr 1985
TL;DR: In this paper, a power supply switching circuit is disclosed which provides for automatically switching an electrical circuit load from a main power source to an auxiliary power source, yet maintaining the two power sources isolated from each other.
Abstract: A power supply switching circuit is disclosed which provides for automatically switching an electrical circuit load from a main power source to an auxiliary power source, yet maintains the two power sources isolated from each other. The power supply switching circuit is readily integrated with its electrical load to form a monolithic integrated circuit. A pair of MOSFETs provides alternate connections of the load to the respective power sources. The circuit effectively connects the gate and source of the appropriate MOSFET across the available power source and thus assures the maximum turn-on voltage is applied to the MOSFET.
TL;DR: In this article, a multilayer PdO-Pd-gate metallization was investigated at a MOS-CO sensor, which gave a high CO sensitivity and a good electrical control of the transistor.
Abstract: A multilayer PdO-Pd-gate metallization was investigated at a MOS-CO sensor. This type of metallization gives a high CO sensitivity and a good electrical control of the transistor. The performance of this sensor was investigated in comparison to a commercial SnO 2 resistor CO sensor.
Patent•
05 Feb 1985
TL;DR: In this paper, a planar enhancement-mode diffused MOSFET structure obviates the source-to-base short conventionally included to prevent turn-on of the parasitic bipolar transistor defined by the main terminal regions of one conductivity type and the intermediate base region of opposite conductivities type, by employing within the base region a recombination region having a relatively small lifetime for excess base region majority-carriers in order to inhibit operation of the bipolar transistor.
Abstract: Power MOSFET devices useful in synchronous rectifier circuit applications are bidirectional and symmetrical for use in AC circuits, and have low on-resistance, fast switching speed, and high voltage capability. In one embodiment, a planar enhancement-mode diffused MOSFET structure obviates the source-to-base short conventionally included to prevent turn-on of the parasitic bipolar transistor defined by the main terminal regions of one conductivity type and the intermediate base region of opposite conductivity type, by employing within the base region a recombination region having a relatively small lifetime for excess base region majority-carriers in order to inhibit operation of the parasitic bipolar transistor. Another embodiment resembles a pair of conventional, vertical-current, MOSFET unit cells formed symmetrically back-to-back and sharing a common drain region which serves only as an intermediate terminal region not directly connected to any device terminal. To inhibit operation of the several parasitic bipolar transistors and thyristor switching device structures inherent in this embodiment, an ohmic short is provided between the source and base regions of each of the unit cells, and a recombination region having a relatively small lifetime for intermediate terminal region majority-carriers is formed within the intermediate terminal region between the spaced base regions of the unit cells.
24 Jun 1985
TL;DR: In this paper, the design and performance of a 10MHz dc/dc converter is discussed and the behavior of the power MOSFET at this frequency, and the integration of device parasitics into the circuit are described.
Abstract: The design and performance of a 10MHz dc/dc converter is discussed. The behavior of the power MOSFET at this frequency, and the integration of device parasitics into the circuit are described. The performance of a 50W converter is compared with the predictions of a detailed simulation. Losses are analysed and shown to be dominated by MOSFET switching.
TL;DR: In this article, an exact solution for the electron distribution as limited by optical phonon scattering is given for an arbitrary shape of potential energy, and current flow, valid for both constant field devices and for the nonconstant fields of a typical metaloxide-semiconductor-field effect transistor (MOSFET) channel in silicon.
Abstract: An exact solution is given in one dimension for the electron distribution as limited by optical phonon scattering. The solution is valid for an arbitrary shape of potential energy, and current flow. Numerical results are presented for both constant field devices, and for the nonconstant fields of a typical metal‐oxide‐semiconductor‐field‐effect transistor (MOSFET) channel in silicon.
TL;DR: In this article, a direct measurement technique for the intrinsic gate capacitances in a small geometry MOS transistor has been developed and is presented in this paper, where the results show that the small MOSFET intrinsic capacitance can be accurately determined using off the self meters, and the use of "on-chip" circuitry is unnecessary.
Abstract: Accurate representation of MOS transistor capacitances is important for accurate circuit simulation. Due to the difficulties of direct measurement with meters, MOS intrinsic capacitances have not been studied extensively. Although several "on-chip" methods have been developed, the need for measurement circuits fabricated alongside the devices of interest seems to be impractical for statistical data generation. In addition, the characterization of both current-voltage ( I-V ) and capacitance-voltage (CV) relationships is not as convenient by using the "on-chip" configurations. Consequently, the direct measurement technique is more desirable than the "on-chip" methods. A direct measurement technique for the intrinsic gate capacitances in a small geometry MOS transistor has been developed and is presented in this letter. By using this method, n-channel transistors with W_{eff}/L_{eff} of, 11/11, 11/2.2, and 11/1.65 µm have been measured. The difference between the long- and short-channel devices can be clearly observed in the measured curves. The results show that the small MOSFET intrinsic capacitances can be accurately determined using off the self meters, and the use of "on-chip" circuitry is unnecessary.
Patent•
29 Nov 1985
TL;DR: In this paper, the authors proposed a method to increase the charge accumulating capacity without increasing space occupied by capacitor by a method wherein several recessions and projections are provided on a semiconductor layer to be one electrode of the capacitor.
Abstract: PURPOSE: To increase the charge accumulating capacity without increasing space occupied by capacitor a substrate by a method wherein several recessions and projections are provided on a semiconductor layer to be one electrode of the capacitor. CONSTITUTION: A MOSFET is formed on a substrate 21 and after depositing a polycrystalline silicon 28 and an oxide film 33 on a drain region 26, unnecessary oxide film is removed leaving necessary part thereof. When a polycrystalline silicon 34 of the same conductive type as that of polycrystalline silicon 28 is deposited on the drain region 26 to be removed by dryetching process, the polycrystalline silicon 34 is left only on the sidewall of oxide film 33 as so-called sidewall. Next, the oxide film 33 only is removed to expose the surface of polycrystalline silicons 28, 34. Then another oxide film 35 is grown in high temperature oxidative atmosphere to form a dielectric film for capacitor. Finally, the other polycrystalline silicon 36 to be the other electrode of capacitor is deposited on overall surface of oxide film 35 to complete the capacitor. COPYRIGHT: (C)1987,JPO&Japio