Showing papers on "Negative impedance converter published in 2018"

Unified Impedance Model of Grid-Connected Voltage-Source Converters

Abstract: This paper proposes a unified impedance model of grid-connected voltage-source converters for analyzing dynamic influences of the phase-locked loop (PLL) and current control. The mathematical relations between the impedance models in the different domains are first explicitly revealed by means of complex transfer functions and complex space vectors. A stationary ( αβ -) frame impedance model is then proposed, which not only predicts the stability impact of the PLL, but also reveals its frequency coupling effect. Furthermore, the impedance shaping effects of the PLL on the current control in the rotating ( dq -) frame and the stationary ( αβ -) frame are structurally comapred. The frequency-domain case studies on a three-phase grid-connected converter are next presented, and subsequently validated in time-domain simulations and experimental tests. The close correlations between the measured results and theoretical analysis confirm the effectiveness of the stationary-frame impedance model.

Steep-slope hysteresis-free negative capacitance MoS 2 transistors

Abstract: The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption 1,2 . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier 3 . Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel 4-12 . Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

A Novel High Step-Up DC–DC Converter With Continuous Input Current Integrating Coupled Inductor for Renewable Energy Applications

Abstract: In this paper, a nonisolated dc–dc converter with high voltage gain is presented. Three diodes, three capacitors, an inductor, and a coupled inductor are employed in the presented converter. Since the inductor is connected to the input, the low input current ripple is achieved, which is important for tracking maximum power point of photovoltaic panels. The voltage stress across switch S is clamped by diode D 1 and capacitor C 1. Therefore, a main switch with low on-resistance RDS (on) can be employed to reduce the conduction loss. Besides, the main switch is turned on under zero current. This reduces the switching loss. The steady-state analysis of the proposed converter is discussed in this paper. Finally, the proposed converter prototype circuit is implemented to justify the validity of the analysis.

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

Abstract: Negative capacitance (NC) FETs with channel lengths from 30 nm to $50~\mu \text{m}$ , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation.

On the stabilization of ferroelectric negative capacitance in nanoscale devices

Abstract: Recently, the proposal to use voltage amplification from ferroelectric negative capacitance (NC) to reduce the power dissipation in nanoelectronic devices has attracted significant attention. Homogeneous Landau theory predicts, that by connecting a ferroelectric in series with a dielectric capacitor, a hysteresis-free NC state can be stabilized in the ferroelectric below a critical film thickness. However, there is a strong discrepancy between experimental results and the current theory. Here, we present a comprehensive revision of the theory of NC stabilization with respect to scaling of material and device dimensions based on multi-domain Ginzburg-Landau theory. It is shown that the use of a metal layer in between the ferroelectric and the dielectric will inherently destabilize NC due to domain formation. However, even without this metal layer, domain formation can reduce the critical ferroelectric thickness considerably, limiting not only the range of NC stabilization, but also the maximum amplification attainable. To overcome these obstacles, the downscaling of lateral device dimensions is proposed as a way to prevent domain formation and to enhance the voltage amplification due to NC. These insights will be crucial for future NC device design and scaling towards nanoscale dimensions.

Interleaved Switched-Capacitor Bidirectional DC-DC Converter With Wide Voltage-Gain Range for Energy Storage Systems

Abstract: In this paper, an interleaved switched-capacitor bidirectional dc-dc converter with a high step-up/step-down voltage gain is proposed. The interleaved structure is adopted in the low-voltage side of this converter to reduce the ripple of the current through the low-voltage side, and the series-connected structure is adopted in the high-voltage side to achieve the high step-up/step-down voltage gain. In addition, the bidirectional synchronous rectification operations are carried out without requiring any extra hardware, and the efficiency of the converter is improved. Furthermore, the operating principles, voltage and current stresses, and current ripple characteristics of the converter are analyzed. Finally, a 1 kW prototype has been developed which verifies a wide voltage-gain range of this converter between the variable low-voltage side (50–120 V) and the constant high-voltage side (400 V). The maximum efficiency of the converter is 95.21% in the step-up mode and 95.30% in the step-down mode. The experimental results also validate the feasibility and the effectiveness of the proposed topology.

Second-Harmonic Current Reduction for Two-Stage Inverter With Boost-Derived Front-End Converter: Control Schemes and Design Considerations

Abstract: The instantaneous output power of the two-stage single-phase inverter pulsates at twice the output frequency $(2f_{{\rm{o}}})$ , generating notorious second-harmonic current (SHC) in the front-end dc–dc converter and the input dc voltage source. This paper focuses on the SHC reduction for a two-stage single-phase inverter with boost-derived front-end converter. To reduce the SHC, a virtual series impedance, which has high impedance at $2f_{{\rm{o}}}$ while low impedance at other frequencies, is introduced in series with the boost diode or the boost inductor to increase the impedance of the boost-diode branch or boost-inductor branch at $2f_{{\rm{o}}}$ . Meanwhile, for achieving good dynamic performance, a virtual parallel impedance, which exhibits infinite impedance at $2f_{{\rm{o}}}$ while low impedance at other frequencies, is introduced in parallel with the dc-bus capacitor to reduce the output impedance of the boost-derived converter at the frequencies except for $2f_{{\rm{o}}}$ . The virtual series impedance is realized by the feedback of the boost-diode current or the boost-inductor current, while the virtual parallel impedance is implemented by the feedback of the dc-bus voltage. Based on the virtual-impedance approach, a variety of SHC reduction control schemes are derived. A step-by-step closed-loop parameters design approach with considerations of reducing the SHC and improving the dynamic performance is also proposed for the derived SHC reduction control schemes. Finally, a 1-kW prototype is built and tested, and experimental results are presented to verify the effectiveness of the proposed SHC reduction control schemes.

The two faces of capacitance: New interpretations for electrical impedance measurements of perovskite solar cells and their relation to hysteresis

Abstract: Perovskite solar cells are notorious for exhibiting transient behavior not seen in conventional inorganic semiconductor devices. Significant inroads have been made into understanding this fact in terms of rapid ion migration, now a well-established property of the prototype photovoltaic perovskite MAPbI 3 and strongly implicated in the newer mixed compositions. Here, we study the manifestations of ion migration in frequency-domain small-signal measurements, focusing on the popular technique of Electrical Impedance Spectroscopy (EIS). We provide new interpretations for a variety of previously puzzling features, including giant photoinduced low-frequency capacitance and negative capacitance in a variety of forms. We show that these apparently strange measurements can be rationalized by the splitting of AC current into two components, one associated with charge-storage and the other with the quasi-steady-state recombination current of electrons and holes. The latter contribution to the capacitance can take either a positive or a negative sign and is potentially very large when slow, voltage-sensitive processes such as ion migration are at play. Using numerical drift-diffusion semiconductor models, we show that giant photoinduced capacitance, inductive loop features, and low-frequency negative capacitance all emerge naturally as consequences of ion migration via its coupling to quasi-steady-state electron and hole currents. In doing so, we unify the understanding of EIS measurements with the comparably well-developed theory of rate dependent current-voltage (I-V) measurements in perovskite cells. Comparing the two techniques, we argue that EIS is more suitable for quantifying I-V hysteresis than conventional methods based on I-V sweeps and demonstrate this application on a variety of cell types.

The Two Faces of Capacitance: New Interpretations for Electrical Impedance Measurements of Perovskite Solar Cells and Their Relation to Hysteresis

Abstract: Perovskite solar cells are notorious for exhibiting transient behaviour not seen in conventional inorganic semiconductor devices. Significant inroads have been made into understanding this fact in terms of rapid ion migration, now a well-established property of the prototype photovoltaic perovskite MAPbI$_3$ and strongly implicated in the newer mixed compositions. Here we study the manifestations of ion migration in frequency-domain small-signal measurements, focusing on the popular technique of Electrical Impedance Spectroscopy (EIS). We provide new interpretations for a variety of previously puzzling features, including giant photo-induced low-frequency capacitance and negative capacitance in a variety of forms. We show that these apparently strange measurements can be rationalized by the splitting of AC current into two components, one associated with charge-storage, and the other with the quasi-steady-state recombination current of electrons and holes. The latter contribution to the capacitance can take either a positive or a negative sign, and is potentially very large when slow, voltage-sensitive processes such as ion migration are at play. Using numerical drift-diffusion semiconductor models, we show that giant photo-induced capacitance, inductive loop features, and low-frequency negative capacitance all emerge naturally as consequences of ion migration via its coupling to quasi-steady-state electron and hole currents. In doing so, we unify the understanding of EIS measurements with the comparably well-developed theory of rate dependent current-voltage (I-V) measurements in perovskite cells. Comparing the two techniques, we argue that EIS is more suitable for quantifying I-V hysteresis than conventional methods based on I-V sweeps, and demonstrate this application on a variety of cell types.

MoS2 Negative‐Capacitance Field‐Effect Transistors with Subthreshold Swing below the Physics Limit

Abstract: The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec-1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec-1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 106 with channel length less than 100 nm. Furthermore, the inserted HfO2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products.

Design and Development of Single Switch High Step-Up DC–DC Converter

Abstract: In this paper, a new single switch high step-up dc–dc converter with high voltage gain is proposed. The proposed topology is developed by combining boost and single-ended primary inductor converter with diode–capacitor circuit to reduce the stress across the semiconductor devices. The proposed converter produces low switching voltage and hence it improves its efficiency. The operating principle and the steady-state performance analysis are discussed. The performance of the converter is validated by developing a prototype circuit with input voltage of 30 V, output voltage of 300 V, and output power rating of 250 W. The theoretical analysis and experimental results conclude the proposed converter that is suitable for high-voltage applications.

A Common Ground Switched-Quasi-$Z$ -Source Bidirectional DC–DC Converter With Wide-Voltage-Gain Range for EVs With Hybrid Energy Sources

Abstract: A common ground switched-quasi- Z -source bidirectional dc–dc converter is proposed for electric vehicles with hybrid energy sources. The proposed converter is based on the traditional two-level quasi- Z -source bidirectional dc–dc converter, changing the position of the main power switch. It has the advantages of a wide-voltage-gain range, a lower voltage stress across the power switches, and an absolute common ground. The operating principle, the voltage and current stresses on the power switches, the comparisons with the other converters, the small signal analysis, and the controller design are presented in this paper. Finally, a 300 W prototype with $U_{{\rm{high}}}= {240 \ \rm{V}}$ and $U_{{\rm{low}}}= {40\sim 120\ \rm{V}}$ is developed, and the experimental results validate the performance and the feasibility of the proposed converter.

Steep-Slope WSe2 Negative Capacitance Field-Effect Transistor

Abstract: P-type two-dimensional steep-slope negative capacitance field-effect transistors are demonstrated for the first time with WSe2 as channel material and ferroelectric hafnium zirconium oxide in gate dielectric stack. F4-TCNQ is used as p-type dopant to suppress electron leakage current and to reduce Schottky barrier width for holes. WSe2 negative capacitance field-effect transistors with and without internal metal gate structures and the internal field-effect transistors are compared and studied. Significant SS reduction is observed in WSe2 negative capacitance field-effect transistors by inserting the ferroelectric hafnium zirconium oxide layer, suggesting the existence of internal amplification (∼10) due to the negative capacitance effect. Subthreshold slope less than 60 mV/dec (as low as 14.4 mV/dec) at room temperature is obtained for both forward and reverse gate voltage sweeps. Negative differential resistance is observed at room temperature on WSe2 negative capacitance field-effect-transistors as the...

An Isolated Multi-Input ZCS DC–DC Front-End-Converter Based Multilevel Inverter for the Integration of Renewable Energy Sources

Abstract: A new isolated current-fed zero-current switched (ZCS) front-end dc/dc converter based multilevel inverter is proposed for multi-input applications. The proposed front-end converter with only two controllable switches integrates two different renewable energy sources, resulting in an advantageous compact structure and low conduction losses. The ZCS turn- off is achieved in both the controllable switches with the proposed modulation scheme. The converter maintains ZCS turn- off under a wide load, as well as input voltage variations by employing frequency modulation along with a variable duty ratio technique. Simple structure, soft switching, high gain, and automatic load regulation make the converter structure novel for simultaneous power management in multi-input renewable energy applications. Converter operation and design guidelines have been outlined. A laboratory prototype of the proposed converter is developed and tested at 300-W power level. Simulations and experimental results demonstrate the robust performance of the converter under load, as well as input source voltage variations.

“Negative capacitance” in resistor-ferroelectric and ferroelectric-dielectric networks: Apparent or intrinsic?

Abstract: In this paper, we describe and analytically substantiate an alternate explanation for the negative capacitance (NC) effect in ferroelectrics (FE). We claim that the NC effect previously demonstrated in resistance-ferroelectric (R-FE) networks does not necessarily validate the existence of “S” shaped relation between polarization and voltage (according to Landau theory). In fact, the NC effect can be explained without invoking the “S”-shaped behavior of FE. We employ an analytical model for FE (Miller model) in which the steady state polarization strictly increases with the voltage across the FE and show that despite the inherent positive FE capacitance, reduction in FE voltage with the increase in its charge is possible in a R-FE network as well as in a ferroelectric-dielectric (FE-DE) stack. This can be attributed to a large increase in FE capacitance near the coercive voltage coupled with the polarization lag with respect to the electric field. Under certain conditions, these two factors yield transient NC effect. We analytically derive conditions for NC effect in R-FE and FE-DE networks. We couple our analysis with extensive simulations to explain the evolution of NC effect. We also compare the trends predicted by the aforementioned Miller model with Landau-Khalatnikov (L-K) model (static negative capacitance due to “S”-shape behaviour) and highlight the differences between the two approaches. First, with an increase in external resistance in the R-FE network, NC effect shows a non-monotonic behavior according to Miller model but increases according to L-K model. Second, with the increase in ramp-rate of applied voltage in the FE-DE stack, NC effect increases according to Miller model but decreases according to L-K model. These results unveil a possible way to experimentally validate the actual reason of NC effect in FE.

Time-Resolved Measurement of Negative Capacitance

Abstract: To reduce the power consumption in scaled CMOS integrated circuits, transistors operating at low supply voltage with steep subthreshold swing (SS) are highly desirable. The negative capacitance (NC) effect in ferroelectric materials has emerged as a possible solution for achieving steep SS in transistors. In order to effectively leverage this effect in device applications, a proper understanding of its time-dependent nature is crucial. Here, we demonstrate that the NC effect occurs within a time window which is bounded by the switching time of ferroelectric domains at the faster time limit and screening charge compensation time of polarization at the slower time limit. We study this temporal dynamics of NC effect both by performing the transient measurements of metal–ferroelectric hafnium zirconium oxide–insulator–semiconductor capacitor connected in series with a load resistor and by characterizing NC field-effect transistors (NCFETs) at different time scales. Our experimental results provide deeper insight into the understanding of NC effect, reveal the time dependent switching nature of NCFETs, and pave way for the advancement of steep-slope transistors technology.

A Bidirectional Resonant DC–DC Converter Suitable for Wide Voltage Gain Range

Abstract: This paper proposes a new bidirectional resonant dc–dc converter suitable for wide voltage gain range applications (e.g., energy storage systems). The proposed converter overcomes the narrow voltage gain range of conventional resonant dc–dc converters, and meanwhile achieves high efficiency throughout the wide range of operation voltage. It is achieved by configuring a full-bridge mode and a half-bridge mode operation during each switching cycle. A fixed-frequency phase-shift control scheme is proposed and the normalized voltage gain can be always from 0.5 to 1, regardless of the load. The transformer root-mean-square (rms) currents in both the forward and reverse power flow directions have a small variation with respect to the voltage gain, which is beneficial to the conduction losses reduction throughout a wide voltage range. Moreover, the power devices are soft-switched for minimum switching losses. The operation principles and characteristics of the proposed converter are firstly analyzed in this paper. Then the analytical solutions for the voltage gain, soft-switching, and rms currents are derived, which facilitates the parameters design and optimization. Finally, the proposed topology and analysis are verified with experimental results obtained from a 1-kW converter prototype.

Ferroelectric negative capacitance domain dynamics

Abstract: Transient negative capacitance effects in epitaxial ferroelectric Pb(Zr0.2Ti0.8)O3 capacitors are investigated with a focus on the dynamical switching behavior governed by domain nucleation and growth. Voltage pulses are applied to a series connection of the ferroelectric capacitor and a resistor to directly measure the ferroelectric negative capacitance during switching. A time-dependent Ginzburg-Landau approach is used to investigate the underlying domain dynamics. The transient negative capacitance is shown to originate from reverse domain nucleation and unrestricted domain growth. However, with the onset of domain coalescence, the capacitance becomes positive again. The persistence of the negative capacitance state is therefore limited by the speed of domain wall motion. By changing the applied electric field, capacitor area or external resistance, this domain wall velocity can be varied predictably over several orders of magnitude. Additionally, detailed insights into the intrinsic material properties of the ferroelectric are obtainable through these measurements. A new method for reliable extraction of the average negative capacitance of the ferroelectric is presented. Furthermore, a simple analytical model is developed, which accurately describes the negative capacitance transient time as a function of the material properties and the experimental boundary conditions.

Physical Origin of Transient Negative Capacitance in a Ferroelectric Capacitor

Abstract: The unusual transient negative differential capacitance (NC) of a resistor--ferroelectric (FE) capacitor circuit is of keen interest for use in next-generation transistors, but a clear physical picture and theoretical framework are needed to interpret experiments. The authors show both numerically and analytically that transient NC comes from the mismatch of free charge and polarization in the capacitor during polarization switching, and a procedure to experimentally determine the viscosity coefficient in Landau theory is provided. These results should have real impact on metrology and device physics involving the NC effect.

Steep switching devices for low power applications: negative differential capacitance/resistance field effect transistors

Abstract: Simply including either single ferroelectric oxide layer or threshold selector, we can make conventional field effect transistor to have super steep switching characteristic, i.e., sub-60-mV/decade of subthreshold slope. One of the representative is negative capacitance FET (NCFET), in which a ferroelectric layer is added within its gate stack. The other is phase FET (i.e., negative resistance FET), in which a threshold selector is added to an electrode (e.g., source or drain) of conventional field effect transistor. Although the concept of the aforementioned two devices was presented more or less recently, numerous studies have been published. In this review paper, by reviewing the published studies over the last decade, we shall de-brief and discuss the history and the future perspectives of NCFET/phase FET, respectively. The background, experimental investigation, and future direction for developing the aforementioned two representative steep switching devices (i.e., NCFET and phase FET/negative resistance FET) are to be discussed in detail.

Design and Analysis of Piezoelectric Metamaterial Beams With Synthetic Impedance Shunt Circuits

Abstract: We present an electromechanical modeling framework and a detailed numerical investigation for the design and analysis of piezoelectric metamaterial beams whose unit cells with segmented electrode pairs are shunted to synthetic impedance circuits. This framework aims to extend the well-studied locally resonant piezoelectric metamaterials and resulting finite metastructures with specified boundary conditions to novel concepts beyond bandgaps associated with simple inductive shunts. Overcoming the bandgap limitations of the locally resonant design requires more advanced considerations in the electrical domain. To this end, we bridge piezoelectric metamaterials and synthetic impedance shunts, and present a general design and analysis framework along with numerical case studies. A general procedure is implemented based on the root locus method for choosing the shunt circuit impedance, with an emphasis on vibration attenuation and practical design considerations. Case studies are presented for systems with locally resonant bandgaps with or without negative capacitance, as well as systems with multiple distinct bandgaps, and the necessary shunt admittance is derived for each case. Simulations are performed for a typical finite meta material beam with synthetic impedance shunts, accounting for the finite sampling rate and circuit dynamics. Time-domain simulations using these synthetic impedance circuits are compared to the ideal frequency-domain results with very good agreement.

Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model

Abstract: In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated.

Impedance-Matching Range Extension Method for Maximum Power Transfer Tracking in IPT System

Abstract: Maximum power transfer is an important index for an inductive power transfer (IPT) system to make full use of its power transfer capability, and such a capability is usually realized by impedance matching. Traditionally, impedance matching is implemented by placing a power electronics converter such as a dc–dc converter at the secondary side of an IPT system. However, the power electronics converter and its operation mode directly affect its impedance-matching range, which is very limited if a traditional power converter only operates at continuous conduction mode (CCM). To extend the impedance-matching range, this paper proposes a novel impedance matching method based on combined CCM and discontinuous conduction mode (DCM) operation of an impedance matching converter. The impedance-matching range is fully analyzed for CCM and DCM operation, respectively, by taking variation of coupling coefficient into consideration. The analysis results show that the impedance-matching range can be extended by more than double that of the traditional impedance matching method. In addition, a maximum power transfer tracking method is developed using the proposed impedance-matching range extension method, and the experimental results have verified the feasibility of the tracking method.

Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor

Abstract: In this paper, we present a surface potential-based explicit continuous model for a metal-ferroelectric-insulator-semiconductor (MFIS) type gate-all-around negative capacitance transistor (GAA-NCFET). Unlike previously reported models, an explicit formulation to calculate the electrical characteristics of GAA-NCFET is proposed. Our model includes the radial dependence of the electric field in the ferroelectric, ignored in the previous works and accurately captures ferroelectric material parameter variations in the nonhysteretic regime. In contrast to bulk NCFETs, GAA-NCFET characteristics show different bias dependence due to the absence of bulk charge. We also present analytical expressions for the terminal charges which are essential to obtain the trans-capacitances for transient simulations. We find that, compared with conventional MOSFETs, the gate charge saturates to a different fraction of its maximum value. Furthermore, the modeling of quantum mechanical effect and overlap capacitances in an MFIS NCFET structure is discussed. Finally, the proposed model has been implemented in Verilog-A and tested for the transient response of ring oscillator in a commercial circuit simulator.

A New Nonisolated High-Voltage-Gain Boost Converter With Inherent Output Voltage Balancing

Abstract: In this paper, a new nonisolated high-voltage-gain boost converter is proposed. The proposed converter is constructed by adding an additional inductor to a conventional three-level-boost (TLB) converter. When compared with the conventional boost and TLB converters, the proposed converter can achieve higher voltage conversion ratio with reduced voltage and current stresses in the switches. In particular, the proposed converter can reduce the losses of active devices by reducing the current of the switch compared to conventional converters, thus, can achieve high efficiency. In addition, the proposed converter automatically balances the output voltages for an unbalanced load without the need for any additional control strategy or auxiliary circuit. A 2-kW prototype converter was built and tested to verify performances of the proposed converter.

On the anomalous peak and negative capacitance in the capacitance–voltage (C–V) plots of Al/(%7 Zn-PVA)/p-Si (MPS) structure

Abstract: The frequency and voltage dependence of the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of the Al/(%7 Zn-doped PVA)/p-Si (MPS) structure were investigated in the wide range of frequency and voltage. Frequency and voltage dependence of C and G/ω shows that these parameters are functions of frequency and voltage. The C–V plot has an anomalous peak and an intersection/crossing point around 1.4 V after which C becomes negative. This negative capacitance (NC) phenomena was attributed to the surface states (Nss), series resistance (Rs) and minority carrier injection. The intensity of NC decreases with increasing frequency and the minimum value of C corresponds to the maximum value of G/ω at strong accumulation region. Whereas the C–V plots have only one peak at low frequencies, they have two peaks at high frequencies due to the special density distribution of Nss and their relaxation time. In addition, the changes in the C and G/ω were attributed to the increase in the polarization and the increased number of carriers in the structure. Impedance method was used for calculation of Rs whereas Nss was obtained using two methods; (i) the high–low frequency capacitance and (ii) Hill-Coleman method as a function of voltage and frequency, respectively. The Fermi energy level (EF), the concentration of doping acceptor atoms (NA) and barrier height (ΦB) values were obtained from reverse bias C−2 vs V plots for each frequency.

Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs

Abstract: We report on measurements and modeling of FE HfZrO/SiO 2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain switching. No traversal of the stabilized negative capacitance branch is required. Modeling is used to correlate the hysteretic properties of the ferroelectric material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon, present only when significant polarization changes occur. The technological implications of this finding are investigated, and it is found that NCFETs are most likely not suitable for high-performance CMOS logic, due to voltage, frequency, and voltage polarity limitations.

An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback

Abstract: This paper presents circuit techniques for ultra-high input impedance analog front end (AFE). In order to boost input impedance, various on- and off-chip parasitic capacitances are cancelled using an active shield and negative capacitance technique. To maximize the cancellation, a self-calibration scheme with active shield replica is proposed for positive feedback-based negative capacitance, which settles at the boundary between stable and unstable states in calibration mode. A prototype IC fabricated in 0.18- $\mu \text{m}$ CMOS achieves an input impedance of 50 $\text{G}\Omega$ at 50 Hz, equivalent to 60-fF capacitance, while consuming 289 nW from 0.8-V supply. The proposed AFE is applied to heart-rate monitoring using 1-cm2 dry electrodes over clothes without any straps.

Negative Capacitance Carbon Nanotube FETs

Abstract: As continued scaling of silicon FETs grows increasingly challenging, alternative paths for improving digital system energy efficiency are being pursued. These paths include replacing the transistor channel with emerging nanomaterials (such as carbon nanotubes), as well as utilizing negative capacitance effects in ferroelectric materials in the FET gate stack, e.g., to improve sub-threshold slope beyond the 60 mV/decade limit. However, which path provides the largest energy efficiency benefits—and whether these multiple paths can be combined to achieve additional energy efficiency benefits—is still unclear. Here, we experimentally demonstrate the first negative capacitance carbon nanotube FETs (CNFETs), combining the benefits of both carbon nanotube channels and negative capacitance effects. We demonstrate negative capacitance CNFETs, achieving sub-60 mV/decade sub-threshold slope with an average sub-threshold slope of 55 mV/decade at room temperature. The average ON-current ( ${I}_{ \mathrm{ON}}$ ) of these negative capacitance CNFETs improves by $2.1\times $ versus baseline CNFETs, (i.e., without negative capacitance) for the same OFF-current ( ${I}_{ \mathrm{OFF}}$ ). This work demonstrates a promising path forward for future generations of energy-efficient electronic systems.