Showing papers on "Parasitic element published in 2013"

Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter

Abstract: The introduction of enhancement mode gallium nitride based power devices such as the eGaN®FET offers the potential to achieve higher efficiencies and higher switching frequencies than possible with Silicon MOSFETs. With the improvements in switching performance and low parasitic packaging provided by eGaN FETs, the PCB layout becomes critical to converter performance. This paper will study the effect of PCB layout parasitic inductance on efficiency and peak device voltage stress for an eGaN FET based point of load (POL) converter operating at a switching frequency of 1 MHz, an input voltage range of 12-28 V, an output voltage of 1.2 V, and an output current up to 20 A. This work will also compare the parasitic inductances of conventional PCB layouts and propose an improved PCB design providing a 40% decrease in parasitic inductance over the best conventional PCB design.

Compact Low-Cost Phased Array of Dielectric Resonator Antenna Using Parasitic Elements and Capacitor Loading

Abstract: A three elements compact low-cost phased array of rectangular dielectric resonator antenna (RDRA) is presented. The scanning phase is based on using mutual coupling and capacitor loading. The center DRA is made of high dielectric constant, er=35.9 and fed by a microstrip line. The two parasitic dielectric resonators (DRs) are electromagnetically coupled to the driven element. The dielectric constant and dimensions of the parasitic element are quite similar to the driven dielectric resonator. The phase shift between elements is adjustable by changing the reactive loading on the parasitic DRs. The reactive loadings are two small capacitors inserted between the microstrip lines and ground plane. The scan coverage of the phased array antenna is ±30 degrees at 2.8 GHz. Across the entire scan angle range, the array return loss is less than 10 dB across a bandwidth of 130 MHz.

Optimization of Integrated Transistors for Very High Frequency DC–DC Converters

Abstract: This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout versus loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50-MHz converter, resulting in a 54% reduction in power loss over a hand-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 3-μm gate length in 20-V design rules is validated at 35 V, offering reduced parasitic resistance and capacitance, as compared to the 5.5-μm device. Compared to the original design, loss is up to 75% lower in the example application.

Impact of parasitic elements on the spurious triggering pulse in synchronous buck converter

Abstract: Limiting the spurious triggering pulse in the gate-source voltage of the lower MOSFET during the turn-on transition of the upper MOSFET is mandatory to prevent substantial switching loss and even shoot-through in the synchronous buck converter. This paper conducts an exhaustive investigation into the impact of the inherent parasitic elements on the spurious triggering pulse to facilitate a reliability-oriented design. An analytical model that considers the parasitic capacitances and inductances, reverse recovery characteristics of the body diode and the interaction between the upper and the lower MOSFETs is established to quantify this pulse. The spurious triggering pulse is found to stem from the induced increase in the gate voltage and the induced decrease in the source voltage. Variation in the magnitude of the spurious triggering pulse in regard to each parasitic element is identified accordingly. Experimental results of a practical synchronous buck converter affirm the theoretical analysis.

Design of Slotted Ground Hexagonal Microstrip Patch Antenna and Gain Improvement with FSS Screen

Abstract: Three hexagonal patch antennas are designed for circular polarization and experimentally validated. These antennas are labeled; simple hexagonal patch, hexagonal patch with slotted ground and hexagonal patch with parasitic element. The measured impedance bandwidths of the three antennas are 2% for the simple patch, 5.2% for the patch with slotted ground and 6.35% for the antenna with parasitic element. The axial ratio (measured) obtained is 4.73% for the patch with slotted ground and 3.33% for the hexagonal patch antenna with parasitic element. The measured radiation patterns of these antennas are found to be in good agreement with the simulated radiation patterns. The average gain of all the three antennas is also evaluated. A frequency selective surface (FSS) is proposed with dimensions smaller than that of a conventional FSS structure. The measured gain improvement with the proposed FSS is around 3dB in the operating band.

Self capacitance touch sensing

Abstract: Self capacitance touch circuits to cancel the effects of parasitic capacitance in a touch sensitive device are disclosed. One circuit can generate a parasitic capacitance cancelation signal that can be injected into touch sensing circuitry to cancel the parasitic capacitance. Another circuit can adjust the phase and magnitude of the parasitic capacitance cancelation signal based on characteristics of channels in the touch sensing circuitry so as to fine tune the parasitic capacitance cancelations. Another circuit can drive a guard plate and touch panel electrodes so as to cancel the parasitic capacitances between the panel and the plate and between the electrodes.

Simulation model development and verification for high voltage GaN HEMT in cascode structure

Abstract: This paper presents the development of a simulation model for high-voltage gallium nitride (GaN) high-electron-mobility transistors (HEMT) in a cascode structure A method is proposed to accurately extract the device package parasitic inductance, which is of vital importance to better predict the high-frequency switching performance of the device The simulation model is verified by a double-pulse tester, and the results match well both in terms of device switching waveform and switching energy Based on the simulation model, an investigation of the package influence on the cascode GaN HEMT is presented, and several critical parasitic inductances are identified and verified Finally, a detailed loss breakdown is made for a buck converter, including a comparison between hard switching and soft switching The results indicate that the switching loss is a dominant part of the total loss in hard-switching conditions in MHz high-frequency range and below 8~10A operation current, therefore soft switching is preferred to achieve high-frequency and high-efficiency operation of the high-voltage GaN HEMT

Electronically reconfigurable beam steering antenna using embedded RF pin based parasitic arrays (ERPPA)

Abstract: In this paper, an electronically reconflgurable beam steering antenna using embedded RF PIN switches based parasitic array (ERPPA) is proposed for modern wireless communication systems that operate at 5.8GHz frequency. In the proposed antenna, a single driven element is fed by a coaxial probe, while each of the two parasitic elements is integrated with an RF PIN switches that embedded inside the substrate. In the conventional reconflgurable antennas, the RF PIN switches are mounted on narrow slots created on the top or bottom layer of the radiator/parasitic elements, which could lead to the dimensional changes of the antenna and degrade the performance in terms of beam steering and return loss. However, this research proposes an exclusive solution where the RF PIN diodes at parasitic elements are embedded inside the substrate thus no additional slots have to be created to mount the SMCs on the antenna. In this regard, the proposed antenna is highly competent to eliminate the intermodulation efiect generated by the RF PIN diodes and the other passive elements associated with the PIN diodes. In this research, extensive investigations revealed that the parasitic element dimension and the selection of RF PIN switches signiflcantly in∞uence

Reconfigurable sum-difference pattern by means of parasitic elements for forward-looking monopulse radar

Abstract: This study describes the design of forward-looking monopulse arrays able to reconfigure the radiation pattern from the sum mode to the difference one by electronically switching a set of parasitic dipoles placed in front of a driven array of radiating dipoles. The antenna architecture is synthesised by optimising the geometric parameters of the passive elements, namely their positions and lengths. The generation of the difference beam is yielded by imposing a phase displacement of π to the excitations of half active array and activating the parasitic array by turning-on the switches that partition their lengths. As for the sum pattern, the effect of the parasitic dipoles is made negligible by turning-off the switches. A set of representative results is reported and discussed to show the effectiveness of the proposed approach.

Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

Abstract: In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asymmetry in structure (between top and bottom electrodes) leads to asymmetric parasitic resistances and capacitances that play an important role in determining the circuit delays. Thus our models help to quantify the role of parasitics on VNW device and CMOS performance having device asymmetry. Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations.

A finite-element analysis approach to determine the parasitic capacitances of high-frequency multiwinding transformers for photovoltaic inverters

Abstract: Magnetic components such as transformers and inductors play a significant role in the efficiency and size/weight of inverter. They are also amongst the most difficult components to design, often requiring numerous design interactions and testing. Understanding and accurate prediction of parasitic winding capacitances of high-frequency multiwinding transformers in PV inverters is fundamental to improve performance, lower cost, and speed time to market. Parasitic capacitances are highly dependent on the winding geometry and the proximity of conducting surfaces. As the geometry of the components becomes more complicated, it is almost impossible to derive analytical equations that describe accurately the behavior of magnetic components. Currently, parasitic capacitances of the multiwinding transformers are only known with certainty once a prototype is built. Therefore a design-build-test cycle needs to be iterated, often at substantial cost and time. This paper presents a technique and method to quantitatively predict the parasitic capacitance of high-frequency multiwinding transformer by means of finite-element analysis (FEA). Comparison of the FEA results with a commercially constructed experimental prototype results shows good agreement.

A FG-MOS Based Fully Differential Current Controlled Conveyor and Its Applications

Abstract: This paper presents a new fully differential second generation current controlled conveyor (FDCCCII) based on differential pair topology, which employs floating gate MOS transistors (FG-MOS). It uses floating gate MOSFETs at the input stage and has rail-to-rail structure which performs with both positive and negative signals. This circuit has tunable parasitic resistance at its input port. It operates with low supply voltage (±0.8 V), low power consumption (lower than 3 mW at current bias of 1 mA), and wide range parasitic resistance (R X ). This circuit has less MOSFET than the previous similar circuits and is suitable for integrated circuit design. To demonstrate the application of the proposed circuit, a fully differential current mode LC-ladder filter and a fully differential multifunction biquad filter are designed. Simulation results by HSPICE confirm validity of the proposed circuit and its application.

Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements

Abstract: We present a schematic transistor model for multifinger multifin FETs, which greatly simplifies an initially complex network. The schematic finFET model accepts various finFET layout information and is accurate in predicting the overall finFET characteristics, including the effect of parasitic resistance (R) and capacitance (C) in a finFET.

Dynamic self-clamping at short-circuit turn-off of high-voltage IGBTs

Abstract: Measurements show that the IGBT is able to clamp the collector-emitter voltage to a certain value at short-circuit turn-off despite a very low gate turn-off resistor in combination with a high parasitic inductance is applied. The IGBT itself reduces the turn-off diC/dt by avalanche injection. However, device destructions during fast turn-off were observed which cannot be linked with an overvoltage failure mode. Measurements and semiconductor simulations of high-voltage IGBTs explain the self-clamping mechanism in detail. Possible failures which can be connected with filamentation processes are described. Options for improving the IGBT robustness during short-circuit turn-off are discussed.

Normally-off GaN switching 400V in 1.4ns using an ultra-low resistance and inductance gate drive

Abstract: A turn-on time of 1.4ns is measured in a normally-off GaN synchronous boost converter switching 400V. The high-speed performance is achieved by significantly improving the GaN switches, packaging and gate drive. A recently developed normally-off, AlN-based insulating-gate, AlGaN/GaN-on-Si HFET operates with a high gate voltage of 6V [1]. The higher gate voltage increases gate current for faster switching. A Multi-Chip-Module (MCM) allows paralleling GaN switch up to 20Arms with low parasitic inductance of ~ 3.6nH in the power loop. The gate drive uses 50mΩ bare MOSFETs integrated onto the MCM to significantly reduce gate driver inductance to 1nH. The very fast switching results in large drain undershoot of 200V, and gate overshoot of more than 6V. Increasing the gate turn-on resistance to 1.4Ω eliminates gate voltage overshoot and reduces drain voltage overshoot to ~20V, at the cost of an increased turn-on time of 3ns.

Parasitic inductance reduction for multilayered board layout designs with semiconductor devices

Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Parasitic Effects on the Performance of DC-DC SEPIC in Photovoltaic Maximum Power Point Tracking Applications

Abstract: This paper presents an analysis of the effect of parasitic resistances on the performance of DC-DC Single Ended Pri- mary Inductor Converter (SEPIC) in photovoltaic maximum power point tracking (MPPT) applications. The energy storage elements incorporated in the SEPIC converter possess parasitic resistances. Although ideal components significantly simplifies model development, but neglecting the parasitic effects in models may sometimes lead to failure in predicting first scale stability and actual performance. Therefore, the effects of parasitics have been taken into consideration for improving the model accuracy, stability, robustness and dynamic performance analysis of the converter. Detail mathematical model of SEPIC converter including inductive parasitic has been developed. The performance of the converter in tracking MPP at different irradiance levels has been analyzed for variation in parasitic resistance. The converter efficiency has been found above 83% for insolation level of 600 W/m2 when the parasitic resistance in the energy storage element has been ignored. However, as the parasitic resistance of both of the inductor has increased to 1 ohm, a fraction of the power managed by the converter has dissipated; as a result the efficiency of the converter has reduced to 78% for the same insolation profile. Although the increasing value of the parasitic has assisted the converter to converge quickly to reach the maximum power point. Furthermore it has also been observed that the peak to peak load current ripple is reduced. The obtained simulation results have validated the competent of the MPPT converter model.

Schottky barrier diode embedded AlGaN/GaN switching transistor

Abstract: We developed a Schottky barrier diode (SBD) embedded AlGaN/GaN switching transistor to allow negative current flow during off-state condition. An SBD was embedded in a recessed normally-off AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistor (MOSHFET). The fabricated device exhibited normally-off characteristics with a gate threshold voltage of 2.8 V, a diode turn-on voltage of 1.2 V, and a breakdown voltage of 849 V for the anode-to-drain distance of 8 µm. An on-resistance of 2.66 mΩcm2 was achieved at a gate voltage of 16 V in the forward transistor mode. Eliminating the need for an external diode, the SBD embedded switching transistor has advantages of significant reduction in parasitic inductance and chip area.

Characterization of density-of-states and parasitic resistance in a-InGaZnO thin-film transistors after negative bias stress

Abstract: Instability mechanism of amorphous InGaZnO thin-film transistors under negative bias stress (NBS) was investigated. After strong NBS stress, we observed a negligible change in the subthreshold swing which is strongly dependent on the subgap density-of-states (DOS). On the other hand, there was substantial increase in the drain current at above-threshold operation. Therefore, the dominant mechanism of the NBS-induced instability is investigated not to be a change in the subgap DOS but a change in the parasitic resistance caused by the reduced Schottky barrier of the metal contacts. This was verified by the extracted source/drain resistance and Technology Computer-Aided Design simulation.

Multilevel power conversion circuit and device

Abstract: [Solution] An actually used flying capacitor-type multilevel power conversion circuit has variations in the characteristics of main semiconductor switches, and includes parasitic elements such as parasitic resistance, parasitic capacity, and parasitic inductance in the circuit, which causes flying capacitors to be charged and discharged to different quantities contrary to ideal case, making it necessary to have voltage sensors for flying capacitor voltage detection and a main semiconductor switch control mechanism in order to suppress fluctuation of the flying capacitor voltages from prescribed values. Furthermore, this circuit becomes unpractical when the number of levels is increased. The present invention provides a circuit that adjusts flying capacitor voltages to prescribed values automatically without voltage sensors for detection of individual flying capacitor voltages, and a main semiconductor switch control mechanism, by additionally providing a main circuit thereof with a closed circuit for suppressing flying capacitor voltage fluctuations by means of an adjusting current.

Antenna system with parasitic element for hearing aid compliant electromagnetic emission

Abstract: A system for production of an electromagnetic (EM) field having EM emissions mitigated at one or more predetermined locations within a Hearing Aid Compliant (HAC) measurement plane is provided. The EM field mitigation system includes a ground plane, an antenna element, and a parasitic resonator element. The antenna element is coupled to the ground plane and resonates within at least one predetermined frequency band for transmitting and receiving the radio frequency (RF) signals modulated at one or more frequencies within the at least one predetermined first frequency band. The parasitic resonator element includes at least a half-wavelength resonator portion floating above the ground plane and a second half-wavelength resonator portion floating above the ground plane, crossing an effective electric field mid-line of the ground plane, and located a predetermined distance from the antenna element for mitigation of the EM emissions of the antenna element at the one or more predetermined locations within the HAC measurement plane.

Analysis of temperature-dependent electrical characteristics in amorphous In-Ga-Zn-O thin-film transistors using gated-four-probe measurements

Abstract: We analyzed the temperature-dependent electrical characteristics of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) using a gated-four-probe method (GFP) with temperatures ranging from 93 to 373 K. The intrinsic field-effect mobility and source/drain parasitic resistance were separately extracted using the GFP method. We found that temperature-dependent transfer characteristics originated from the temperature-dependent intrinsic field-effect mobility of the a-IGZO TFTs. The parasitic resistance was also correlated with the intrinsic-field effect mobility, which decreases as the intrinsic field-effect mobility increases, indicating that access parasitic resistance originated from bulk regions rather than metal/semiconductor junction barrier is a key factor to determine the parasitic resistance of a-IGZO TFTs.

Low package parasitic inductance using a thru-substrate interposer

Abstract: An interposer for a chipset includes multilayer thin film capacitors incorporated therein to reduce parasitic inductance in the chipset. Power and ground terminals are laid out in a staggered pattern to cancel magnetic fields between conductive vias to reduce equivalent series inductance (ESL).

Experimental study of parasitic inductance influence on SiC MOSFET switching performance in Matrix converter

Abstract: This paper presents an experimental parametric study of parasitic inductance influence on SiC MOSFET switching waveforms in matrix converter. The two most critical parasitic inductances have been studied and compared in terms of their effect on waveform ringing, switching loss and device stress. Knowledge about the effects of parasitic inductances on the switching behavior serves as an important basis for the design guideline of fast switching matrix converter.

Analytical prediction of switching losses in MOSFETs for variable drain-source voltage and current applications

Abstract: This paper presents an analytical modeling of a MOSFET during switching operation, aimed at determining the switching losses. Moreover it compares the theoretical results with experimental data. The switching losses are calculated for different DC link voltages and load currents. The stray inductances and capacitances of the MOSFET were considered in the modeling. Besides the parasitic inductance in the circuit was calculated from the measurement and was applied in the loss modeling. It is shown that the switching waveforms obtained from the measurement are in agreement with the simulation results. However, due to the limitations of the drive circuit, the driver circuit output gate signal registered in the measurements had to be used in the simulations.

Measuring circuit for capacitance and parasitic resistance of capacitor

Abstract: A measuring circuit for a capacity and a parasitic resistance of a capacitor includes a voltage switching circuit, a charging circuit, a discharging and sampling circuit and a control circuit, wherein the charging circuit is used for charging the capacitor to be measured; the discharging and sampling circuit is used for receiving an output voltage of the voltage switching circuit, controlling the discharging of the capacitor to be measured and detecting the voltage of the capacitor to be measured and the voltage of a discharge resistor; and the control circuit comprises a microprocessor with a timer, the microprocessor receives a control signal output by the charging circuit to control the charging circuit to stop charging, outputs a discharge control signal to control the capacitor to be measured to discharge, controls the discharging and sampling circuit to obtain the discharge time of the capacitor to be measured, calculates according to the discharge time and the resistance value of the discharge resistor to obtain the capacity of the capacitor to be measured, and controls the discharging and sampling circuit to detect the voltage of the capacitor to be measured and the voltage of the discharge resistor to obtain the parasitic resistance value of the capacitor to be measured according to the acquired voltage and the resistance value of the discharge resistor. The measuring circuit for the capacity and the parasitic resistance of the capacitor can measure accurately.

Complete model of parasitic capacitances in a cascade voltage multiplier in the high voltage generator

Abstract: Symmetry Cockcroft Walton multiplier is a typical cascade voltage multiplier. It is an attractive alternative to the high voltage (HV) transformer with high turn ratio and bridge rectifier in the HV generator in medical X-ray machine. It can reduce the stray capacitance of the HV transformer. However, previous work reports that the parasitic capacitances in the multiplier itself can be added to the stray capacitance of the transformer, which becomes a burden to the resonant capacitance of the generator. Thus, it is crucial to minimize the parasitic capacitances in the multiplier. In this paper, the complete model of the parasitic capacitances in the multiplier is exhibited. The model gives full description of parasitic capacitances in any spatial configuration of the multiplier module. Then, the equivalent capacitance of the model is obtained and analyzed to exhibit the role of parasitic capacitances in the system circuit. The dependence of the equivalent capacitance on different parameters, such as different groups of parasitic capacitances and the number of diodes per chain, is addressed. Besides, the impact of breakdown of the diodes on the equivalent capacitance is also exhibited. The complete capacitance model and the analysis of the equivalent parasitic capacitance are validated by the experimental measurements. In the end, guidelines are concluded for how to minimize the equivalent parasitic.

Stability in Small Signal Common Base Amplifiers

Abstract: This paper presents an analytical study of parasitic oscillation in video bandwidth common base amplifiers. We develop a series of progressively more complex small signal equivalent circuits based on the hybrid-π model [1], [2]. These circuits are developed such that the effect of each new parasitic element on circuit performance is evident. The conditions required for negative input resistance are developed for each equivalent circuit in turn. A general design `rule' of τL <; τT for stability is proposed. The common base amplifier is also treated as a Colpitts oscillator. Conditions required for stability are developed by assessing the conditions necessary for instability. The effect of employing `base stopper' resistors is also explored. Finally some general guidance on the successful layout of video bandwidth circuits is given.