Showing papers on "Spice published in 2002"

IC Interconnect Analysis

Abstract: Preface. 1. Introduction. 2. The Elmore Delay. 3. Higher-Order RC(L) Delay Metrics. 4. Asymptotic Waveform Evaluation. 5. Moment Generation. 6. Passive Reduced-Order Multiport Models. 7. Interfacing with SPICE. 8. Interfacing Interconnect and Gate-Delay Models. Index.

Parametric macromodels of digital I/O ports

Abstract: Addresses the development of macromodels for input and output ports of a digital device. The proposed macromodels consist of parametric representations that can be obtained from port transient waveforms at the device ports via a well established procedure. The models are implementable as SPICE subcircuits and their accuracy and efficiency are verified by applying the approach to the characterization of transistor-level models of commercial devices.

Comparison of SETs in bipolar linear circuits generated with an ion microbeam, laser light, and circuit simulation

Abstract: Generally good agreement is obtained between the single-event output voltage transient waveforms obtained by exposing individual circuit elements of a bipolar comparator and operational amplifier to an ion microbeam, a pulsed laser beam, and circuit simulations using SPICE. The agreement is achieved by adjusting the amounts of charge deposited by the laser or injected in the SPICE simulations. The implications for radiation hardness assurance are discussed.

Studying the impact of gate tunneling on dynamic behaviors of partially-depleted SOI CMOS using BSIMPD

Abstract: In this, work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests that gate tunneling has a strong impact on the delay range and should be considered in SOI circuit simulation. It is crucial for circuit, designers to understand and contain the hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism should be used to quantify the effect without undermining the performance benefit of a partially depleted SOI technology. BSIMPD is one model that attempts to bridge the gap between advanced SOI technologies and circuit design. With its built-in floating-body, self-heating and body-contact modules, BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI chips. BSIMPD has been implemented in Berkeley SPICE3f4 and other commercial SPICE simulators. It may also be the basis for computing the look-up tables used for higher-level timing simulation.

Improved Spice models of aluminum electrolytic capacitors for inverter applications

Abstract: Impedance modeling of aluminum electrolytic capacitors presents a challenge to design engineers, due to the complex nature of the capacitor construction Unlike an electrostatic capacitor, an electrolytic capacitor behaves like a lossy coaxial distributed RC circuit element whose series and distributed resistances are strong functions of temperature and frequency This behavior gives rise to values of capacitance, ESR (effective series resistance), and impedance that vary by several orders of magnitude over the typical frequency and temperature range of power inverter applications Existing public-domain Spice models do not accurately account for this behavior In this paper, a physics-based approach is used to develop an improved impedance model that is interpreted both in pure Spice circuit models and in math functions

Signal integrity analysis system

Abstract: A method of signal integrity analysis includes providing a pre-defined circuit layout in SPICE format; selecting from a menu at least one of a technology, a driver, a driver package, a transmission line, a termination, a receiver package, a stimulus, a measurement, options, and sweep parameters for the predefined circuit layout; generating a SPICE netlist from the pre-defined circuit layout; simulating the predefined circuit layout from the SPICE netlist; and generating as output at least one of a listing, a waveform, and a signal measurement from the simulation of the pre-defined circuit layout.

A new compact DC model of floating gate memory cells without capacitive coupling coefficients

Abstract: This paper presents for the first time a new compact SPICE model of floating gate nonvolatile memory cells capable to reproduce effectively the complete DC electrical behavior in every bias conditions. This model features many advantages compared to previous ones: it is simple and easy to implement since it uses SPICE circuit elements, is scalable, and its computational time is not excessive. It is based on a new procedure that calculates the floating gate voltage without using fixed capacitive coupling coefficients, thus improving the floating gate voltage estimate that is fundamental for the correct modeling of cell operations. Moreover, this model requires only the usual parameters adopted for SPICE-like models of MOS transistors plus the floating gate-control gate capacitance, making it very attractive to industry as the same parameter extraction procedure used for MOS transistors can be directly applied. The model we propose has been validated on E/sup 2/PROM and flash memory cells manufactured in existing technology (0.35 /spl mu/m and 0.25 /spl mu/m) by STMicroelectronics.

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

Abstract: A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.

Synthesis of SPICE-compatible broadband electrical models from n-port scattering parameter data

Abstract: In this paper, an efficient technique for the synthesis of broadband electrical models from multiport scattering parameter data (S-parameter) is presented. A curve fitting algorithm is applied to either measured or simulated S-parameters to generate a frequency-dependent transfer-function matrix representation of the system of interest. By means of macromodel synthesis techniques an equivalent circuit network, consisting of standard circuit elements, is derived from the transfer-function matrix representation. The synthesized networks are compatible with SPICE-based circuit simulators, as demonstrated by numerical examples for a two-port and a four-port system. The proposed method is suitable for the analysis of S-parameter based linear sub-networks in a general circuit environment consisting of lumped/distributed elements and nonlinear devices.

Parameters estimation of the d.c. electrothermal model of the bipolar transistor

Abstract: This paper concerns the problems of the parameter values estimation of d.c. electrothermal model of the BJT formulated for circuit analysis with SPICE. In this case, PARTS software available in SPICE cannot be used. In the paper, a new estimation algorithm for d.c. electrothermal model of the BJT is proposed. The form of the electrothermal BJT model is also presented. The estimation algorithm implemented into the computer-controlled measurement set allows one to derive the values of the parameters automatically after the measurements of the selected isothermal characteristics and proper calculations. Copyright © 2002 John Wiley & Sons, Ltd.

Universal CMOS current-mode analog function synthesizer

Abstract: A CMOS integratable current-mode analog function synthesizer circuit is presented. The proposed circuit is based on approximating the required function using the first three terms of its Taylor series expansion. These approximations can be implemented by adding the output currents of a weighted current square, a weighted current amplifier (or attenuator) and a constant current. The proposed circuit can simultaneously realize 18 different mathematical functions and can be easily expanded to accommodate others. SPICE simulation results demonstrating the circuit performance are included.

Advanced SPICE modeling of large power IGBT modules

Abstract: An enhanced insulated gate bipolar transistor (IGBT) model based on the Kraus model with new derivations based on an extra parameter accounting for p-i-n injection was developed to allow simulation of both trench and DMOS IGBT structures. Temperature dependence was also implemented in the model. The model was validated against steady-state and transient measurements done on an 800-A 1.7-kV Dynex IGBT module at 25/spl deg/C and 125/spl deg/C. The Spice model has also shown excellent agreement with mixed mode MEDICI simulations. The Spice model also takes into account for the first time the parasitic thyristor effect allowing the dc and dynamic temperature-dependent latchup modeling of power modules as well as their temperature-dependent safe operating area.

Modeling of the CoolMOS/sup TM/ transistor. II. DC model and parameter extraction

Abstract: An accurate dc model for the CoolMOS/sup TM/ power transistor is presented. An elementary model consisting of an intrinsic MOSFET and a JFET to represent the drift region, is first discussed and it is pointed out that this is a rather poor model, needing improvements. Using device simulation results, it is shown that, by replacing the gate and drain voltages of the intrinsic MOSFET by appropriate "effective" voltages, a highly accurate model is obtained. A systematic procedure for parameter extraction is described and an implementation of the new model in the form of a SPICE subcircuit is given.

A decoupling method for analysis of coupled RLC interconnects

Abstract: In this paper we present an efficient decoupling model for on-chip interconnect analysis. This model decouples multiple RLC transmission lines into independent lines with separate drivers and receivers. Based on this model we propose an efficient algorithm to solve the far end responses of multiple RLC lines. Experiments show good matching between our decoupling model and SPICE simulation. Based on the model, we further develop an Nmax algorithm to quickly determine the noise amplitudes of far end responses. Experiments show that Nmax algorithm gives conservative but reasonably accurate results compared to SPICE simulation.

Simultaneous switching noise and resonance analysis of on-chip power distribution network

Abstract: This paper presents a frequency-domain technique for finding the worst-case time-domain voltage variations in the RLC power bus of digital VLSI circuits. Pattern independent maximum envelope currents are used for the logic gates and macroblocks. The voltage drop/surge at a power bus node is expressed in term of the currents using sensitivity analysis. The sensitivity information together with an optimization procedure are applied to find the upper-bounds on the voltage variations at the targeted bus nodes. The resonance problem due to the on-chip RLC power distribution network is analyzed base on the frequency-domain sensitivity analysis. Comparisons to SPICE simulation of circuits extracted from layouts are used to validate our approach.

A TLM-SPICE interconnection framework for coupled field and circuit analysis in the time domain

Abstract: A general SPICE-transmission-line matrix (TLM) interconnection framework has been developed. The connection algorithm is based on the representation of the TLM network by equivalent Thevenin and/or Norton sources. Fundamental issues such as source equivalence and SPICE-TLM interconnection options have been examined. The framework opens new and far-reaching possibilities for hybrid global microwave and high-speed digital circuit modeling in the time domain because it combines the extensive circuit and device models of SPICE with general three-dimensional field solutions.

Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method

Abstract: This paper presents a method for analyzing multilayered power distribution networks in the frequency domain. Using a two dimensional array of distributed RLCG circuits, multi-layered power distribution planes are represented. Each plane pair is connected by vias, which are modeled as partial self and mutual inductors. For the efficient computation of the power distribution impedances at specific points in the network, a multiinput and multi-output transmission matrix method has been used, which is much faster than Spice and reduces memory requirements. This method has been compared with the cavity resonator method simulated in Spice.

Compact spice grinder

Abstract: A compact and efficient spice grinder having a centrally disposed post configured for engaging a spice seed in the grinding chamber. The spice seed is initially “fractured” by a “pestle-like” seed fracturing structuring at the top of the post. When a user thereafter rotates the dome-like cover of the grinder with respect to the base, spice fragments are grated against interior blades positioned along the sidewall of the chamber adapter/extender. A dome cover is gradually lowered by a user as the spice in the grinding chamber becomes depleted. The grinder is lightweight and may be attached conveniently to a key ring or to a chain and carried as a novelty item.

A low distortion MOS sampling circuit

Abstract: This paper presents a sampling technique with reduced distortion for use in a sample-and-hold circuit for high resolution analog-to-digital converters and switched capacitor filters. The technique involves bootstrapping both the gate and the bulk terminal of the sampling switch to improve linearity. Circuit implementation and SPICE level simulation results are presented.

A SPICE-compatible model for nanoscale MOSFET capacitor simulation under the inversion condition

Abstract: A SPICE-compatible charge model for nanoscale MOSFET is proposed. Based on the solution of Schrodinger-Poisson (S-P) equations, the developed compact charge model is optimized with respect to: 1) the position of the charge concentration peak; 2) the maximum of the charge concentration; 3) the total inversion charge sheet density; and 4) the average inversion charge depth, respectively. This model can predict inversion layer electron density for various oxide thicknesses and applied voltages. Compared to the S-P results, our model prediction is within 5% of accuracy. Application of this charge quantization model to the C-V measurement produces an excellent agreement. This compact model has continuous derivatives and is therefore amenable to a device simulator. It can also be easily incorporated into circuit simulator for modeling ultrathin oxide MOSFET C-V characteristics.

A Complete Phase-Locked Loop Power Consumption Model

Abstract: Summary form only given. A PLL power model that accurately estimates the power consumption during both lock and acquisition states is presented. The model is within 5% of circuit level simulation (SPICE) values. No significant power overhead (+/-5% of the power consumed at the final frequency) is incurred during the acquisition process.

Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Abstract: Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient i>IR voltage drops within a power distribution network. These transient i>IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient i>IR voltage drops are presented in this paper. The peak value of these transient i>IR voltage drops is within 6% as compared to SPICE. Circuit- and layout-level design constraints are also discussed to manage the peak value of the transient i>IR voltage drops. The propagation delay of a CMOS logic gate based on these analytical expressions is within 5% of SPICE while the estimate without considering transient i>IR voltage drops can exceed 20% for a 20 Ω power line.

Modeling of the CoolMOS™ Transistor—Part II: DC Model and Parameter Extraction

Abstract: An accurate dc model for the CoolMOS™ power transistor is presented. An elementary model consisting of an intrinsic MOSFET and a JFET to represent the drift region, is first discussed and it is pointed out that this is a rather poor model, needing improvements. Using device simulation results, it is shown that, by replacing the gate and drain voltages of the intrinsic MOSFET by appropriate "effective" voltages, a highly accurate model is obtained. A systematic procedure for parameter extraction is described and an implementation of the new model in the form of a SPICE subcircuit is given.

New CMOS configurations for current-controlled conveyors (CCCIIs)

Abstract: In this paper two new CMOS configurations for current-controlled conveyor (CCCII) are proposed. The proposed circuits provide good linearity, very high input impedance at port-y, high output impedance at port Z and good input/output current gain. SPICE simulation results using TUBITAK 3 /spl mu/ CMOS process model are included to verify the expected values.

Method and apparatus for custom design in a standard cell design environment

Abstract: Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be converted to circuit functions and corresponding standard cells are then selected. The SPICE netlist is employed to define timing paths. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of the SPICE simulation. The present invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is converted to a Verilog standard cell netlist. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells in the Verilog netlist and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of SPICE simulations.

A surface-based integral-equation formulation for coupled electromagnetic and circuit simulation

Abstract: A surface-based integral-equation formulation for coupled electromagnetic and circuit simulation is presented. The approach is sufficiently general to model arbitrarily shaped structures and high-frequency skin effects. The formulation is implemented in both an equivalent circuit form for spice compatibility, and in a more general form as a coupled-matrix system outside spice. The overall approach can be interpreted as either a modified surface-only partial element equivalent circuit approach, or as a circuit-coupled version of the surface-based method of moments. © 2002 Wiley Periodicals, Inc. Microwave Opt Technol Lett 34: 103–106, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.10386

A Simple Thermal and Electrical Model of an Infrared Pyroelectric Detector Using Spice

Abstract: This paper shows a complete description of a simple infrared pyroelectric detector model, using SPICE. Both thermal and electrical properties of the detector model have been implemented in order to simulate the detector response versus time and frequency for any radiation stimulus. The detector model has been designed to obtain Ý v and NEP. The effect of the material properties of the detector on its response has been studied. The parameters of the proposed model may be adjusted to the experimental response of the detector, although not all of its properties are known. From this adjustment a good approximation of those unknown properties is deduced. Good agreement has been found between simulated and measured results.

Equivalent circuit approach for single electron transistor model for efficient circuit simulation by SPICE

Abstract: A new compact DC/transient single electron transistor model for circuit simulation by SPICE is introduced. This model includes a newly developed equivalent circuit approach based on the time-dependent master equation and an exact conductance or transconductance model. The simulation speed of this model is improved, compared with that of the previous models.

A 1.5 V CCII-based tunable oscillator for portable industrial applications

Abstract: In this paper a low-voltage CCII-based tunable oscillator is presented. The circuit makes use of new first and second generation current conveyors, designed to operate at typical supply voltages as low as 1.5 V, the minimum being 1.2 V. SPICE simulations, performed by 0.5 mm CMOS process from ALCATEL-MIETEC, well confirm the theoretical analysis. In particular, CCI and CCII models have been taken into account. Simulation results give a large tuning range (7-9.5 MHz), a total harmonic distortion lower than 1.5% and a 530 mW power consumption at 1.5 V supply.