Proceedings ArticleDOI
A scalable processing-in-memory accelerator for parallel graph processing
Junwhan Ahn,Sungpack Hong,Sungjoo Yoo,Onur Mutlu,Kiyoung Choi +4 more
- Vol. 43, Iss: 3, pp 105-117
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TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.Abstract:
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.read more
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Proceedings ArticleDOI
Architecting Waferscale Processors - A GPU Case Study
TL;DR: It is shown that while a 300 mm wafer can house about 100 GPU modules (GPM), only a much scaled down GPU architecture with about 40 GPMs can be built when physical concerns are considered, and developed thread scheduling and data placement policies for waferscale GPU architectures.
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Substream-Centric Maximum Matchings on FPGA
TL;DR: This work proposes the first maximum matching algorithm designed for FPGAs; it is energy-efficient and has provable guarantees on accuracy, performance, and storage utilization, and proposes a substream-centric approach, in which the input stream of data is divided into substreams processed independently to enable more parallelism while lowering communication costs.
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A Novel ReRAM-Based Processing-in-Memory Architecture for Graph Traversal
TL;DR: This work proposes a new ReRAM-based processing-in-memory architecture called RPBFS, in which graph data can be persistently stored and processed in place and shows a significant performance improvement compared with both the CPU-based and the GPU-based BFS implementations.
Proceedings ArticleDOI
NATSA: A Near-Data Processing Accelerator for Time Series Analysis
Iván López Fernández,Ricardo Quislant,Eladio Gutierrez,Oscar Plata,Christina Giannoula,Mohammed Alser,Juan Gómez-Luna,Onur Mutlu +7 more
TL;DR: NATSA as mentioned in this paper is the first near-data processing accelerator for time series analysis, which exploits modern 3D-stacked High Bandwidth Memory (HBM) to enable efficient and fast specialized matrix profile computation near memory.
Proceedings ArticleDOI
Massively parallel skyline computation for processing-in-memory architectures
TL;DR: The first skyline algorithm for PIM architectures, called DSky, is designed to be massively parallel and throughput efficient by leveraging a novel work assignment strategy that emphasizes load balancing and achieves 2× to 14× higher throughput compared to the state-of-the-art solutions on competing CPU and GPU architectures.
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