Proceedings ArticleDOI
A scalable processing-in-memory accelerator for parallel graph processing
Junwhan Ahn,Sungpack Hong,Sungjoo Yoo,Onur Mutlu,Kiyoung Choi +4 more
- Vol. 43, Iss: 3, pp 105-117
TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.Abstract:
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.read more
Citations
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Proceedings ArticleDOI
Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning Predictors
TL;DR: In this paper, a machine learning framework is proposed to predict the performance of near-data processing (NDP) applications on 3D-stacked DRAM systems, based on an input set of application characteristics.
Proceedings ArticleDOI
XORiM: a case of in-memory bit-comparator implementation and its performance implications
TL;DR: This work proposes XORiM, an inexpensive PIM design to achieve fast bulky bitwise XOR operation in commodity DRAM devices for memory-intensive workloads and demonstrates the application of XO-RiM to realistic workloads by conducting full-system level simulation.
Proceedings ArticleDOI
MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows
Siying Feng,Xin He,Kuan-Yu Chen,Liu Ke,Xuan Zhang,David Blaauw,Trevor Mudge,Ronald G. Dreslinski +7 more
TL;DR: MeNDA is a scalable near-DRAM multi-way merge accelerator that eliminates the off-chip memory interface bottleneck and exposes the high internal memory bandwidth to improve performance and reduce energy consumption for sparse matrix transposition.
Journal ArticleDOI
Microarchitectural Attacks in Heterogeneous Systems: A Survey
TL;DR: This survey article considers the security of heterogeneous systems against microarchitectural attacks, with a focus on covert- and side-channel attacks, as well as fault injection attacks.
Journal ArticleDOI
Effective runtime scheduling for high-performance graph processing on heterogeneous dataflow architecture
TL;DR: This paper proposes a novel runtime system that can adaptively offload each subgraph to an appropriate underlying architecture and presents a hybrid execution model to drive optimal performance.
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