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Proceedings ArticleDOI

A scalable processing-in-memory accelerator for parallel graph processing

TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.
Abstract
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.

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In-memory multiplication engine with SOT-MRAM based stochastic computing

TL;DR: A new stochastic computing (SC) design to perform MUL with in-memory operations is proposed, which provides up to 4x improvement in performance compared with conversational SC approaches, and achieves 18x speedup over implementing Mul with only in- memory bitwise Boolean logic operations.

GraphIA: an in-situ accelerator for large-scale graph processing.

TL;DR: GraphIA as discussed by the authors is an in-situ accelerator for large-scale graph processing based on DRAM technology, which couples large-capacity memory and computing resource in DRAM by connecting multiple chips with computation circuits inside.
Posted Content

Application-Driven Near-Data Processing for Similarity Search

TL;DR: The Similarity Search Associative Memory (SSAM) as discussed by the authors is an application-driven near-data processing accelerator for similarity search, which can achieve up to two orders of magnitude area-normalized throughput and energy efficiency improvement over multicore CPUs.
Posted Content

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism.

TL;DR: This paper summarizes the idea of Subarray-Level Parallelism (SALP) in DRAM, which was published in ISCA 2012, and examines the work's significance and future potential, and proposes three new mechanisms, SALP-1, SALp-2, and MASA (Multitude of Activated Subarrays), to reduce the serialization of different requests that go to the same bank.
Proceedings ArticleDOI

Ultra Efficient Acceleration for De Novo Genome Assembly via Near-Memory Computing

TL;DR: Zhang et al. as mentioned in this paper proposed a near-data processing (NDP) architecture based on 3D-stacking, which distributes key operations across NDP cores to exploit high degree of parallelism and high memory bandwidth.
References
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Journal Article

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Sergey Brin, +1 more
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Journal ArticleDOI

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Proceedings ArticleDOI

Pregel: a system for large-scale graph processing

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