Proceedings ArticleDOI
A scalable processing-in-memory accelerator for parallel graph processing
Junwhan Ahn,Sungpack Hong,Sungjoo Yoo,Onur Mutlu,Kiyoung Choi +4 more
- Vol. 43, Iss: 3, pp 105-117
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TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.Abstract:
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.read more
Citations
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Proceedings ArticleDOI
Exploiting Near-Data Processing to Accelerate Time Series Analysis
Ivan Fernandez,Ricardo Quislant,Christina Giannoula,Mohammed Alser,Juan G'omez-Luna,Eladio Gutierrez,Oscar Plata,Onur Mutlu +7 more
TL;DR:
Journal ArticleDOI
Triple Engine Processor (TEP): A Heterogeneous Near-Memory Processor for Diverse Kernel Operations
Hong-Yeol Lim,Gi-Ho Park +1 more
TL;DR: This analysis confirms that three categories of processing engines for NMP logic are required for efficient processing of a variety of emerging applications, and thus a Triple Engine Processor (TEP) is proposed, a heterogeneous near-memory processor with three types of computing engines.
Proceedings ArticleDOI
Gearbox: a case for supporting accumulation dispatching and hybrid partitioning in PIM-based accelerators
TL;DR: A highly parallel architecture that can exploit the available parallelism even in the presence of random accesses is proposed and a dispatching mechanism for remote accumulation offloading is introduced.
Posted Content
Platform Independent Software Analysis for Near Memory Computing
TL;DR: PISA-NMC as mentioned in this paper extends a state-of-the-art hardware agnostic profiling tool with metrics concerning memory and parallelism, which are relevant for NMC.
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Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins
Donghyuk Lee,Yoongu Kim,Gennady Pekhimenko,Samira Khan,Vivek Seshadri,Kevin K. Chang,Onur Mutlu +6 more
TL;DR: This paper summarizes the idea of Adaptive-Latency DRAM, which was published in HPCA 2015, and examines the work's significance and future potential, and characterizes the extra margin that is built into the DRAM timing parameters.
References
More filters
Journal ArticleDOI
The anatomy of a large-scale hypertextual Web search engine
Sergey Brin,Lawrence Page +1 more
TL;DR: This paper provides an in-depth description of Google, a prototype of a large-scale search engine which makes heavy use of the structure present in hypertext and looks at the problem of how to effectively deal with uncontrolled hypertext collections where anyone can publish anything they want.
Journal Article
The Anatomy of a Large-Scale Hypertextual Web Search Engine.
Sergey Brin,Lawrence Page +1 more
TL;DR: Google as discussed by the authors is a prototype of a large-scale search engine which makes heavy use of the structure present in hypertext and is designed to crawl and index the Web efficiently and produce much more satisfying search results than existing systems.
Journal ArticleDOI
A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs
George Karypis,Vipin Kumar +1 more
TL;DR: This work presents a new coarsening heuristic (called heavy-edge heuristic) for which the size of the partition of the coarse graph is within a small factor of theSize of the final partition obtained after multilevel refinement, and presents a much faster variation of the Kernighan--Lin (KL) algorithm for refining during uncoarsening.
Journal ArticleDOI
Pin: building customized program analysis tools with dynamic instrumentation
Chi-Keung Luk,Robert Cohn,Robert Muth,Harish Patil,Artur Klauser,Geoff Lowney,Steven Wallace,Vijay Janapa Reddi,Kim Hazelwood +8 more
TL;DR: The goals are to provide easy-to-use, portable, transparent, and efficient instrumentation, and to illustrate Pin's versatility, two Pintools in daily use to analyze production software are described.
Proceedings ArticleDOI
Pregel: a system for large-scale graph processing
Grzegorz Malewicz,Matthew H. Austern,Aart J. C. Bik,James C. Dehnert,Ilan Horn,Naty Leiser,Grzegorz Czajkowski +6 more
TL;DR: A model for processing large graphs that has been designed for efficient, scalable and fault-tolerant implementation on clusters of thousands of commodity computers, and its implied synchronicity makes reasoning about programs easier.