Proceedings ArticleDOI
A scalable processing-in-memory accelerator for parallel graph processing
Junwhan Ahn,Sungpack Hong,Sungjoo Yoo,Onur Mutlu,Kiyoung Choi +4 more
- Vol. 43, Iss: 3, pp 105-117
TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.Abstract:
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.read more
Citations
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Proceedings ArticleDOI
SparseMEM: Energy-efficient Design for In-memory Sparse-based Graph Processing
TL;DR: In this paper , the authors proposed SparseMEM, a graph processing accelerator targeting sparse datasets by leveraging the computing-in-memory (CIM) concept; CIM is a promising solution to alleviate the overhead of data movement and the inherent poor locality of graph processing.
Journal ArticleDOI
ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems
Nika Mansouri Ghiasi,Nandita Vijaykumar,Geraldo F. Oliveira,Lois Orosa,Ivan Fernandez,Mohammad Sadrosadati,Konstantinos Kanellopoulos,Nastaran Hajinazar,Juan Gómez Luna,Onur Mutlu +9 more
TL;DR: A programmer-transparent technique to alleviate the inter-segment data movement overhead between host and memory in near-data processing (NDP) systems is proposed in this article .
Journal ArticleDOI
Access pattern-based high-performance main memory system for graph processing on single machines
TL;DR: This paper presents a high-capacity main memory system with an intelligent pattern-aware prefetching engine to overcome the scalability problem and the memory inefficiency of single-machine graph processing.
Book ChapterDOI
X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs
Sven Rheindt,Andreas Fried,Oliver Lenke,Lars Nolte,Temur Sabirov,Tim Twardzik,Thomas Wild,Andreas Herkersdorf +7 more
TL;DR: X-CEL is proposed, a method to accurately estimate the potential of near- memory acceleration using an easy-to-integrate near-memory core and showcases its benefits with three variants of graph copy mechanisms in a tile-based MPSoC.
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