Proceedings ArticleDOI
A scalable processing-in-memory accelerator for parallel graph processing
Junwhan Ahn,Sungpack Hong,Sungjoo Yoo,Onur Mutlu,Kiyoung Choi +4 more
- Vol. 43, Iss: 3, pp 105-117
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TLDR
This work argues that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve memory-capacity-proportional performance and designs a programmable PIM accelerator for large-scale graph processing called Tesseract.Abstract:
The explosion of digital data and the ever-growing need for fast data analysis have made in-memory big-data processing in computer systems increasingly important. In particular, large-scale graph processing is gaining attention due to its broad applicability from social science to machine learning. However, scalable hardware design that can efficiently process large graphs in main memory is still an open problem. Ideally, cost-effective and scalable graph processing systems can be realized by building a system whose performance increases proportionally with the sizes of graphs that can be stored in the system, which is extremely challenging in conventional systems due to severe memory bandwidth limitations. In this work, we argue that the conventional concept of processing-in-memory (PIM) can be a viable solution to achieve such an objective. The key modern enabler for PIM is the recent advancement of the 3D integration technology that facilitates stacking logic and memory dies in a single package, which was not available when the PIM concept was originally examined. In order to take advantage of such a new technology to enable memory-capacity-proportional performance, we design a programmable PIM accelerator for large-scale graph processing called Tesseract. Tesseract is composed of (1) a new hardware architecture that fully utilizes the available memory bandwidth, (2) an efficient method of communication between different memory partitions, and (3) a programming interface that reflects and exploits the unique hardware design. It also includes two hardware prefetchers specialized for memory access patterns of graph processing, which operate based on the hints provided by our programming model. Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.read more
Citations
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Proceedings ArticleDOI
Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads
TL;DR: An in-depth data-type-aware characterization of graph processing workloads on a simulated multi-core architecture finds that the load-load dependency chains involving different application data types form the primary bottleneck in achieving a high memory-level parallelism.
Proceedings ArticleDOI
GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing
Shaahin Angizi,Deliang Fan +1 more
TL;DR: The extensive circuit-architecture simulations over three social network data-sets indicate that GraphiDe achieves on average 3.1x energy-efficiency improvement and 4.2x speed-up over the recent DRAM based PIM platform.
Proceedings ArticleDOI
Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach
Mingyu Yan,Xing Hu,Shuangchen Li,Abanti Basak,Han Li,Xin Ma,Itir Akgun,Yujing Feng,Peng Gu,Lei Deng,Xiaochun Ye,Zhimin Zhang,Dongrui Fan,Yuan Xie +13 more
TL;DR: This work proposes GraphDynS, a hardware/software co-design with decoupled datapath and data-aware dynamic scheduling that can elaborately schedule the program on-the-fly to maximize parallelism and extract data dependencies at runtime.
Proceedings ArticleDOI
APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures
TL;DR: APPROX-NoC is proposed, a hardware data approximation framework with an online data error control mechanism for high performance NoCs that facilitates approximate matching of data patterns, within a controllable value range, to compress them thereby reducing the volume of data movement across the chip.
Journal ArticleDOI
A Survey on Graph Processing Accelerators: Challenges and Opportunities
TL;DR: In this article, the authors conduct a systematical survey regarding the design and implementation of graph processing accelerators and present and discuss several challenges in details, and further explore the opportunities for the future research.
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