High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture
Sarah H. Olsen,Anthony O'Neill,L.S. Driscoll,K.S.K. Kwa,Sanatan Chattopadhyay,A.M. Waite,Y.T. Tang,A.G.R. Evans,D. J. Norris,A. G. Cullis,Douglas J. Paul,D. J. Robbins +11 more
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TLDR
In this paper, a novel layer structure comprising Si/Si/sub 0.7/Ge/Sub 0.3/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure.Abstract:
Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.read more
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Journal ArticleDOI
Si/SiGe heterostructures: from material and physics to devices and circuits
TL;DR: In this paper, the authors present a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system, in particular, the important device technologies in mainstream microelectronics.
Patent
Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
TL;DR: In this article, the authors describe a method for fabricating FETs with impurity-free regions of the strained material layers of the semiconductor, where the impurities are kept free of impurities that can interdiffuse from adjacent portions of the FET.
Journal ArticleDOI
integrations and challenges of novel high-k gate stacks in advanced cmos technology
TL;DR: In this article, the authors review the current status and challenges in novel high-k dielectrics and metal gates research for planar CMOS devices and alternative device technologies to provide insights for future research.
Journal ArticleDOI
Film thickness constraints for manufacturable strained silicon CMOS
J.G. Fiorenza,G. Braithwaite,C. W. Leitz,Matthew T. Currie,J. Yap,F. Singaporewala,V. K. Yang,T. A. Langdo,John A. Carlin,Mark Somerville,Anthony Lochtefeld,H. Badawi,Mayank T. Bulsara +12 more
TL;DR: In this article, the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates was studied. And the mechanism of the leakage was examined by using photon emission microscopy.
Journal ArticleDOI
Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs
Goutam Kumar Dalapati,Sanatan Chattopadhyay,K.S.K. Kwa,Sarah H. Olsen,Y.L. Tsang,R Agaiby,Anthony O'Neill,P. Dobrosz,Steve Bull +8 more
TL;DR: In this article, the performance of a surface channel Si n-MOSFET is significantly influenced by the strained Si/SiO/sub 2/ interface quality, and the effect of the interface trap density was found to be proportional to the Ge content in the virtual substrate.
References
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TL;DR: In this paper, it was shown that the interfaces between layers were made up of large coherent areas separated by long straight misfit dislocations and the Burgers vectors were inclined at 45° to (001) and were of type 1/2a.
Book
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TL;DR: In this article, the authors present a method for extracting interface trap properties from the conductance of a metal oxide Silicon Capacitor at intermediate and high frequency intervals, and demonstrate that these properties can be used for charge trapping in the oxide.
MOS /metal oxide semiconductor/ physics and technology
TL;DR: In this article, the authors present a method for extracting interface trap properties from the conductance of a metal oxide Silicon Capacitor at intermediate and high frequency intervals, and demonstrate that these properties can be used for charge trapping in the oxide.
Journal ArticleDOI
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.