Journal ArticleDOI
Impact of High- $k$ Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs
C.R. Manoj,Valipe Ramgopal Rao +1 more
TLDR
In this paper, the impact of high-k gate dielectrics on device short-channel and circuit performance of fin field effect transistors is studied over a wide range of dielectric permittivities.Abstract:
The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance Cof in addition to an increase in the internal fringe capacitance Cif with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineeringread more
Citations
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Journal ArticleDOI
Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Journal ArticleDOI
Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization
TL;DR: In this paper, the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions was studied and the use of high-kappa spacers to enhance the effect of GFIBL and thereby achieve better device and circuit performance.
Journal ArticleDOI
Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)
Vadthiya Narendar,R. A. Mishra +1 more
TL;DR: In this article, a 3D analytical modeling of SOI multigate (GAA), triple-gate (TG), double-gate and double-Gate (DG) FinFETs is presented.
Journal ArticleDOI
Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs
Mehdi Salmani-Jelodar,Hesameddin Ilatikhameneh,Sungguen Kim,Kwok Ng,Prasad Sarangapani,Gerhard Klimeck +5 more
TL;DR: In this article, the effects of using high-k oxides and gate stacks on the performance of ultrascaled metal oxide semiconductor field effect transistors ( mosfet s) are analyzed.
Journal ArticleDOI
Investigation of Symmetric Dual-k Spacer Trigate FinFETs From Delay Perspective
TL;DR: In this article, an improvised symmetric dual-k spacer (SymD-k) underlap trigate FinFET architecture is employed for the purpose of reducing the fringe capacitance effect.
References
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Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI
Analysis of the parasitic S/D resistance in multiple-gate FETs
TL;DR: In this article, the authors analyzed the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, s/D geometry-based analytical model, which was validated using three-dimensional device simulations and experimental results.
Journal ArticleDOI
The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs
Baohong Cheng,Min Cao,R. Rao,A. Inani,P. Vande Voorde,Wayne Greene,J.M.C. Stork,Zhiping Yu,P.M. Zeitzoff,Jason C. S. Woo +9 more
TL;DR: In this paper, the potential impact of high/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2D) simulator implemented with quantum mechanical models.
Journal ArticleDOI
Modeling and optimization of fringe capacitance of nanoscale DGMOS devices
TL;DR: In this paper, the impact of gate electrode thickness and gate underlap on the fringe capacitance of double-gate MOS transistors was analyzed and an analytical model was proposed to estimate the marginal capacitance.
Journal ArticleDOI
Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization
TL;DR: In this paper, a wideband experimental and three-dimensional simulation analyses have been carried out to compare the analog/RF performance of planar double-gate (DG), triple-gate, Fin-FET, Pi-Gate (PG), and single-gate SOI MOSFETs.