Journal ArticleDOI
Limits on Silicon Nanoelectronics for Terascale Integration
TLDR
Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip.Abstract:
Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.read more
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Journal ArticleDOI
Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems
Andrea C. Ferrari,Francesco Bonaccorso,Francesco Bonaccorso,Vladimir I. Fal'ko,Konstantin S. Novoselov,Stephan Roche,Peter Bøggild,Stefano Borini,Frank H. L. Koppens,Vincenzo Palermo,Nicola M. Pugno,Nicola M. Pugno,Nicola M. Pugno,Jose A. Garrido,Roman Sordan,Alberto Bianco,Laura Ballerini,Maurizio Prato,Elefterios Lidorikis,Jani Kivioja,Claudio Marinelli,Tapani Ryhänen,Alberto F. Morpurgo,Jonathan N. Coleman,Valeria Nicolosi,Luigi Colombo,Albert Fert,Albert Fert,Mar García-Hernández,Adrian Bachtold,Grégory F. Schneider,Francisco Guinea,Cees Dekker,Matteo Barbone,Zhipei Sun,Costas Galiotis,Alexander N. Grigorenko,Gerasimos Konstantatos,Andras Kis,Mikhail I. Katsnelson,Lieven M. K. Vandersypen,A. Loiseau,Vittorio Morandi,Daniel Neumaier,Emanuele Treossi,Vittorio Pellegrini,Vittorio Pellegrini,Marco Polini,Alessandro Tredicucci,Gareth M. Williams,Byung Hee Hong,Jong Hyun Ahn,Jong Min Kim,Herbert Zirath,Bart J. van Wees,Herre S. J. van der Zant,Luigi Occhipinti,Andrea di Matteo,Ian A. Kinloch,Thomas Seyller,Etienne Quesnel,Xinliang Feng,K.B.K. Teo,Nalin Rupesinghe,Pertti Hakonen,Simon R. T. Neil,Quentin Tannock,Tomas Löfwander,Jari M. Kinaret +68 more
TL;DR: An overview of the key aspects of graphene and related materials, ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries are provided.
BookDOI
Converging technologies for improving human performance
TL;DR: This report incorporates the views expressed at the workshop of leading experts from government, academia, and private sector, and detailed in contributions submitted thereafter by members of the U.S. science and engineering community.
Journal ArticleDOI
Digital processing and communication with molecular switches
TL;DR: In this paper, the three basic logic operations (AND, NOT, and OR) and more complex logic functions (EOR, INH, NOR, XNOR, and XOR) have been reproduced already at the molecular level.
Journal ArticleDOI
Scaling carbon nanotube complementary transistors to 5-nm gate lengths
TL;DR: High-performance top-gated carbon nanotube field-effect transistors with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale.
References
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Journal ArticleDOI
Low power microelectronics: retrospect and prospect
TL;DR: In this paper, the authors argue that future opportunities for low power gigascale integration will be governed by a hierarchy of theoretical and practical limits whose levels can be codified as: (1) fundamental, (2) material, (3) device, (4) circuit, and (5) system.
Journal ArticleDOI
A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation
TL;DR: A rigorous derivation of a complete wire-length distribution for on-chip random logic networks is performed and a methodology to calculate the wire- length distribution for future gigascale integration (GSI) products is proposed.