Proceedings ArticleDOI
MOSFETs with 9 to 13 A thick gate oxides
M.S. Krishnan,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +3 more
- pp 241-244
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TLDR
In this paper, an improved methodology of gate oxide thickness extraction from the MOSFET gate currents in the accumulation regime is proposed, and experimental evidence for a mobility reduction mechanism, namely Remote Charge Scattering, has been presented.Abstract:
In this work, NMOSFETs with gate oxides between 9 to 13 A have been fabricated and its behavior analyzed. An improved methodology of extracting gate oxide thickness from the MOSFET gate currents in the accumulation regime is proposed. Experimental evidence for a mobility reduction mechanism, namely Remote Charge Scattering, has been presented. The mobility was found to be degraded because of scattering by ionized impurities in the poly-gate.read more
Citations
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Journal ArticleDOI
Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling
Wen-Chin Lee,Chenming Hu +1 more
TL;DR: In this paper, a semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1-3.6 nm) as a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N/sup +/, P/sup+/, Si, SiGe) and tunneling processes.
Journal ArticleDOI
Material and process limits in silicon VLSI technology
TL;DR: Some of the the most challenging materials and process issues to be faced in the future are described and where possible solutions are known, describes these potential solutions.
Journal ArticleDOI
Modeling of electron mobility degradation by remote Coulomb scattering in ultrathin oxide MOSFETs
David Esseni,Antonio Abramo +1 more
TL;DR: In this paper, a model for the remote Coulomb scattering (RCS) in ultrathin gate oxide MOSFETs due to ionized impurities in the polysilicon is presented.
Journal ArticleDOI
Vertically scaled MOSFET gate stacks and junctions: how far are we likely to go?
Carlton M. Osburn,I. Kim,S. K. Han,I. De,K. F. Yee,S. Gannavaram,S. J. Lee,C. H. Lee,Z. J. Luo,Wenjuan Zhu,Jay Hauser,D.-L. Kwong,Gerald Lucovsky,T. P. Ma,Mehmet C. Öztürk +14 more
TL;DR: The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed and it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage.
Patent
Apparatus and method for multiple-gate semiconductor device with angled sidewalls
TL;DR: In this article, a process for fabricating a FinFET includes the steps of etching a silicon-on-insulator wafer to form an active region, including the source, channel, and drain, with vertically angled sidewalls.
References
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CMOS scaling into the nanometer regime
Yuan Taur,Douglas A. Buchanan,Wei Chen,David J. Frank,Khalid EzzEldin Ismail,Shih-Hsien Lo,George Anthony Sai-Halasz,R. Viswanathan,Hsing-Jen Wann,Shalom J. Wind,Hon-Sum Philip Wong +10 more
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Journal ArticleDOI
1.5 nm direct-tunneling gate oxide Si MOSFET's
Hiroki Sasaki,Mizuki Ono,Takashi Yoshitomi,Tatsuya Ohguro,S. Nakamura,Masanobu Saito,Hiroshi Iwai +6 more
TL;DR: In this paper, a 1.5 nm direct-tunneling gate oxide was used to achieve a transconductance of more than 1,000 mS/mm at a gate length of 0.09 /spl mu/m at room temperature.
Journal ArticleDOI
Analytic model for direct tunneling current in polycrystalline silicon-gate metal–oxide–semiconductor devices
TL;DR: In this paper, an analytic model of the direct tunneling current in metal-oxide-semiconductor devices as a function of oxide field is presented, and accurate modeling of the low-field roll-off in the current results from proper modeling of field dependencies of the sheet charge, electron impact frequency on the interface, and tunneling probability.
Journal ArticleDOI
Mechanism of leakage current through the nanoscale SiO2 layer
TL;DR: In this article, the mechanism of leakage current through the nanoscale ultrathin silicon dioxide (SiO2) layer in a metal-insulator-semiconductor structure based on the multiple scattering theory was clarified.
Proceedings ArticleDOI
Remote charge scattering in MOSFETs with ultra-thin gate dielectrics
TL;DR: In this paper, the authors studied the mobility degradation of inversion charge due to remote charge scattering (RCS), referring to scattering of mobile charges in the inversion layer by charged impurities present in the gate material of a MOSFET.